From patchwork Fri Mar 17 06:46:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9629901 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B4C4E602D7 for ; Fri, 17 Mar 2017 06:48:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A539028698 for ; Fri, 17 Mar 2017 06:48:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9A2952869B; Fri, 17 Mar 2017 06:48:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 259B12869F for ; Fri, 17 Mar 2017 06:48:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1colep-0000Ts-Cy; Fri, 17 Mar 2017 06:46:39 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coleo-0000Qz-9U for xen-devel@lists.xen.org; Fri, 17 Mar 2017 06:46:38 +0000 Received: from [85.158.143.35] by server-11.bemta-6.messagelabs.com id CC/B8-04971-E468BC85; Fri, 17 Mar 2017 06:46:38 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRWlGSWpSXmKPExsVywNxEW9e37XS Ewbu/EhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bFudNZCs4ZVJzdfIS1gXG1ahcjJ4eQQIXE 1f4PzCC2hACvxJFlM1gh7ACJ4wsvM3UxcgHV9DJK3Ll6ix0kwSagL7Hi8UGwIhEBaYlrny8zg tjMAtUSE6fPAbOFBXwlGretAKthEVCVuLJ9MguIzStgK7HhzDMmiAXyEheungKLcwrYSXxsvM UCcZCtRGPDbaYJjLwLGBlWMWoUpxaVpRbpGhrqJRVlpmeU5CZm5ugaGpjp5aYWFyemp+YkJhX rJefnbmIEhgMDEOxg/LQs4BCjJAeTkihv58lTEUJ8SfkplRmJxRnxRaU5qcWHGGU4OJQkeJ+1 nI4QEixKTU+tSMvMAQYmTFqCg0dJhPceSJq3uCAxtzgzHSJ1ilFRSpz3FkhCACSRUZoH1waLh kuMslLCvIxAhwjxFKQW5WaWoMq/YhTnYFQS5n0CMoUnM68EbvoroMVMQIvffjgBsrgkESEl1c C4kGGWF5t0zuEqhmzejq0pl9ymTJCXueZ1r2kX2/6TX3gzzgc6Srd+qdJflPztgWDO7Nk7O6+ HcFtNMhEUP3/4cPCSTRK9LhxBawLfvZfqF3x790jruz2xXbXbtp49cOVk40vPqbwlVw9zfHkt EvA5QW5S5vYZ/JEysR3sWZ55FT2xU6L11C4qsRRnJBpqMRcVJwIAgeHoHIECAAA= X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-2.tower-21.messagelabs.com!1489733194!48828732!1 X-Originating-IP: [192.55.52.43] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 56999 invoked from network); 17 Mar 2017 06:46:37 -0000 Received: from mga05.intel.com (HELO mga05.intel.com) (192.55.52.43) by server-2.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Mar 2017 06:46:37 -0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP; 16 Mar 2017 23:46:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,175,1486454400"; d="scan'208"; a="1109452608" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by orsmga001.jf.intel.com with ESMTP; 16 Mar 2017 23:46:35 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Fri, 17 Mar 2017 14:46:07 +0800 Message-Id: <20170317064614.23539-6-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170317064614.23539-1-haozhong.zhang@intel.com> References: <20170317064614.23539-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH v2 05/12] x86/mce_intel: detect and enable LMCE on Intel host X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Enable LMCE if it's supported by the host CPU. If Xen boot parameter "mce_fb = 1" is present, LMCE will be disabled forcibly. Signed-off-by: Haozhong Zhang Reviewed-by: Jan Beulich --- Cc: Jan Beulich Cc: Andrew Cooper Changes in v2: * (By patch 1) Convert all bool_t to bool, and use true and false. * Fix the check of MSR_IA32_FEATURE_CONTROL in intel_enable_lmce(). * (By patch 2) Adjust the output messages of MCA capabilities. * For additions in existing function, use the coding style around. For new added functions, use the coding style of Xen hypervisor. --- xen/arch/x86/cpu/mcheck/mce.h | 1 + xen/arch/x86/cpu/mcheck/mce_intel.c | 46 ++++++++++++++++++++++++++++++++----- xen/arch/x86/cpu/mcheck/x86_mca.h | 5 ++++ xen/include/asm-x86/msr-index.h | 2 ++ 4 files changed, 48 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 9347eb9..ec58a91 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -38,6 +38,7 @@ enum mcheck_type { }; extern uint8_t cmci_apic_vector; +extern bool lmce_support; /* Init functions */ enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *c); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index fe927f6..f8cf5e6 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -29,6 +29,9 @@ boolean_param("mce_fb", mce_force_broadcast); static int __read_mostly nr_intel_ext_msrs; +/* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */ +bool __read_mostly lmce_support; + /* Intel SDM define bit15~bit0 of IA32_MCi_STATUS as the MC error code */ #define INTEL_MCCOD_MASK 0xFFFF @@ -704,10 +707,34 @@ static bool mce_is_broadcast(struct cpuinfo_x86 *c) return false; } +static bool intel_enable_lmce(void) +{ + uint64_t msr_content; + + /* + * Section "Enabling Local Machine Check" in Intel SDM Vol 3 + * requires software must ensure the LOCK bit and LMCE_ON bit + * of MSR_IA32_FEATURE_CONTROL are set before setting + * MSR_IA32_MCG_EXT_CTL.LMCE_EN. + */ + + if ( rdmsr_safe(MSR_IA32_FEATURE_CONTROL, msr_content) ) + return false; + + if ( (msr_content & IA32_FEATURE_CONTROL_LOCK) && + (msr_content & IA32_FEATURE_CONTROL_LMCE_ON) ) + { + wrmsrl(MSR_IA32_MCG_EXT_CTL, MCG_EXT_CTL_LMCE_EN); + return true; + } + + return false; +} + /* Check and init MCA */ static void intel_init_mca(struct cpuinfo_x86 *c) { - bool broadcast, cmci = false, ser = false; + bool broadcast, cmci = false, ser = false, lmce = false; int ext_num = 0, first; uint64_t msr_content; @@ -727,33 +754,40 @@ static void intel_init_mca(struct cpuinfo_x86 *c) first = mce_firstbank(c); + if (!mce_force_broadcast && (msr_content & MCG_LMCE_P)) + lmce = intel_enable_lmce(); + #define CAP(enabled, name) ((enabled) ? ", "name : "") if (smp_processor_id() == 0) { dprintk(XENLOG_INFO, - "MCA Capability: firstbank %d, extended MCE MSR %d%s%s%s\n", + "MCA Capability: firstbank %d, extended MCE MSR %d%s%s%s%s\n", first, ext_num, CAP(broadcast, "BCAST"), CAP(ser, "SER"), - CAP(cmci, "CMCI")); + CAP(cmci, "CMCI"), + CAP(lmce, "LMCE")); mce_broadcast = broadcast; cmci_support = cmci; ser_support = ser; + lmce_support = lmce; nr_intel_ext_msrs = ext_num; firstbank = first; } else if (cmci != cmci_support || ser != ser_support || broadcast != mce_broadcast || - first != firstbank || ext_num != nr_intel_ext_msrs) + first != firstbank || ext_num != nr_intel_ext_msrs || + lmce != lmce_support) dprintk(XENLOG_WARNING, "CPU %u has different MCA capability " - "(firstbank %d, extended MCE MSR %d%s%s%s)" + "(firstbank %d, extended MCE MSR %d%s%s%s%s)" " than BSP, may cause undetermined result!!!\n", smp_processor_id(), first, ext_num, CAP(broadcast, "BCAST"), CAP(ser, "SER"), - CAP(cmci, "CMCI")); + CAP(cmci, "CMCI"), + CAP(lmce, "LMCE")); #undef CAP } diff --git a/xen/arch/x86/cpu/mcheck/x86_mca.h b/xen/arch/x86/cpu/mcheck/x86_mca.h index de03f82..0f87bcf 100644 --- a/xen/arch/x86/cpu/mcheck/x86_mca.h +++ b/xen/arch/x86/cpu/mcheck/x86_mca.h @@ -36,6 +36,7 @@ #define MCG_TES_P (1ULL<<11) /* Intel specific */ #define MCG_EXT_CNT 16 /* Intel specific */ #define MCG_SER_P (1ULL<<24) /* Intel specific */ +#define MCG_LMCE_P (1ULL<<27) /* Intel specific */ /* Other bits are reserved */ /* Bitfield of the MSR_IA32_MCG_STATUS register */ @@ -46,6 +47,10 @@ /* Bits 3-63 are reserved on CPU not supporting LMCE */ /* Bits 4-63 are reserved on CPU supporting LMCE */ +/* Bitfield of MSR_IA32_MCG_EXT_CTL register (Intel Specific) */ +#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) +/* Other bits are reserved */ + /* Bitfield of MSR_K8_MCi_STATUS registers */ /* MCA error code */ #define MCi_STATUS_MCA 0x000000000000ffffULL diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 771e750..756b23d 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -51,6 +51,7 @@ #define MSR_IA32_MCG_CAP 0x00000179 #define MSR_IA32_MCG_STATUS 0x0000017a #define MSR_IA32_MCG_CTL 0x0000017b +#define MSR_IA32_MCG_EXT_CTL 0x000004d0 #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 @@ -296,6 +297,7 @@ #define IA32_FEATURE_CONTROL_SENTER_PARAM_CTL 0x7f00 #define IA32_FEATURE_CONTROL_ENABLE_SENTER 0x8000 #define IA32_FEATURE_CONTROL_SGX_ENABLE 0x40000 +#define IA32_FEATURE_CONTROL_LMCE_ON 0x100000 #define MSR_IA32_TSC_ADJUST 0x0000003b