From patchwork Thu Mar 23 11:46:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anthony PERARD X-Patchwork-Id: 9640913 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A8D3B602D6 for ; Thu, 23 Mar 2017 11:49:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 977B5284A5 for ; Thu, 23 Mar 2017 11:49:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8BF6C284CB; Thu, 23 Mar 2017 11:49:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 25009284A5 for ; Thu, 23 Mar 2017 11:49:32 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cr1D8-0003Nx-9s; Thu, 23 Mar 2017 11:47:22 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cr1D7-0003NR-54 for xen-devel@lists.xenproject.org; Thu, 23 Mar 2017 11:47:21 +0000 Received: from [85.158.137.68] by server-3.bemta-3.messagelabs.com id C1/50-14551-8C5B3D85; Thu, 23 Mar 2017 11:47:20 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeJIrShJLcpLzFFi42JxWrrBXvfE1ss RBn3XGS2+b5nM5MDocfjDFZYAxijWzLyk/IoE1oyu73OZCs4ZVmxee5qxgbFXqYuRk0NCwF9i +d8GFhCbTcBAYsX0q4xdjBwcIgIqErf3GoCEmQWqJR61tTKC2MICvhIf3rSzgtgsAqoSxxqOg tm8AnYSh9ZeY4cYKS+xaNMMsJGcAvYSt1vfgMWFgGoWfm9gg7DVJG4sXMYC0SsocXLmExaIXR ISB1+8YJ7AyDsLSWoWktQCRqZVjBrFqUVlqUW6hkZ6SUWZ6RkluYmZObqGBsZ6uanFxYnpqTm JScV6yfm5mxiBocMABDsYX3U7H2KU5GBSEuUt/3EiQogvKT+lMiOxOCO+qDQntfgQowwHh5IE rzJITrAoNT21Ii0zBxjEMGkJDh4lEd7LIGne4oLE3OLMdIjUKUZFKXFeGZCEAEgiozQPrg0WO ZcYZaWEeRmBDhHiKUgtys0sQZV/xSjOwagkzJsKMoUnM68EbvoroMVMQIvffgBbXJKIkJJqYP R++Er6vL3Jauf/O/jefayRc/+qv2fPH1X29Yc2V1gxdTx8xc3XdWHLkaRmx5f3bjQ8S53U5ba 8tGzaZdOj/203CMlsreExaYjmL96atfuHZuDJVzcbGsxzra2jFKtmmz/f8HHHkrzNBWI+k4IT L+zY3nCH4eQndqncmA+z4q9VJsZsy0zaUKjEUpyRaKjFXFScCAB5sPJ6lwIAAA== X-Env-Sender: prvs=248b8503f=anthony.perard@citrix.com X-Msg-Ref: server-13.tower-31.messagelabs.com!1490269638!91062029!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 39288 invoked from network); 23 Mar 2017 11:47:19 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-13.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 23 Mar 2017 11:47:19 -0000 X-IronPort-AV: E=Sophos;i="5.36,209,1486425600"; d="scan'208";a="424361830" From: Anthony PERARD To: Date: Thu, 23 Mar 2017 11:46:59 +0000 Message-ID: <20170323114701.25207-2-anthony.perard@citrix.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170323114701.25207-1-anthony.perard@citrix.com> References: <20170323114701.25207-1-anthony.perard@citrix.com> MIME-Version: 1.0 Cc: Anthony PERARD , Andrew Cooper , Jan Beulich Subject: [Xen-devel] [PATCH 1/3] x86/vlapic: Fix vLAPIC Timer to behave more like real-hw X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch takes care of change of timer mode between periodic and one-shot, because the timer is not reset this happen. There is still change of the Divide Configuration Register that is not handle by this patch, but will be in: x86/vlapic: Handle change of timer Divide Configuration Register Testing has been done with XTF+(patch "Add vlapic timer checks"). Signed-off-by: Anthony PERARD --- xen/arch/x86/hvm/vlapic.c | 113 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 83 insertions(+), 30 deletions(-) diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 14356a78fe..97b7774b61 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -518,7 +518,11 @@ static uint32_t vlapic_get_tmcct(struct vlapic *vlapic) counter_passed = ((hvm_get_guest_time(v) - vlapic->timer_last_update) / (APIC_BUS_CYCLE_NS * vlapic->hw.timer_divisor)); - if ( tmict != 0 ) + /* If timer_last_update is 0, then TMCCT should be 0 as well. + * This happen when the timer is set to periodic with TMICT != 0, but TMCCT + * was already down to 0. + */ + if ( tmict != 0 && vlapic->timer_last_update ) { if ( vlapic_lvtt_period(vlapic) ) counter_passed %= tmict; @@ -666,6 +670,82 @@ static void vlapic_tdt_pt_cb(struct vcpu *v, void *data) vcpu_vlapic(v)->hw.tdt_msr = 0; } +static void vlapic_update_timer(struct vlapic *vlapic, + unsigned int offset, + uint32_t val) +{ + + uint64_t period; + uint64_t delta = 0; + bool is_oneshot, is_periodic; + + switch (offset) + { + case APIC_LVTT: + period = (uint64_t)vlapic_get_reg(vlapic, APIC_TMICT) + * APIC_BUS_CYCLE_NS * vlapic->hw.timer_divisor; + is_periodic = (val & APIC_TIMER_MODE_MASK) == APIC_TIMER_MODE_PERIODIC; + is_oneshot = (val & APIC_TIMER_MODE_MASK) == APIC_TIMER_MODE_ONESHOT; + + /* Calculate the next time the timer should trigger an interrupt. */ + if ( period && vlapic->timer_last_update ) + { + uint64_t time_passed = hvm_get_guest_time(current) + - vlapic->timer_last_update; + if ( vlapic_lvtt_period(vlapic) ) + time_passed %= period; + if ( time_passed < period ) + delta = period - time_passed; + } + break; + case APIC_TMICT: + period = (uint64_t)val * APIC_BUS_CYCLE_NS * vlapic->hw.timer_divisor; + delta = period; + + is_periodic = vlapic_lvtt_period(vlapic); + is_oneshot = vlapic_lvtt_oneshot(vlapic); + break; + default: + BUG(); + } + + if ( (is_oneshot || is_periodic) && delta != 0 ) + { + TRACE_2_LONG_3D(TRC_HVM_EMUL_LAPIC_START_TIMER, TRC_PAR_LONG(delta), + TRC_PAR_LONG(is_periodic ? period : 0LL), + vlapic->pt.irq); + + create_periodic_time(current, &vlapic->pt, + delta, + is_periodic ? period : 0, + vlapic->pt.irq, + is_periodic ? vlapic_pt_cb : NULL, + &vlapic->timer_last_update); + + /* For the case where the timer was periodic and it is now + * one-shot, timer_last_update should be the value of the last time + * the interrupt was triggered. + */ + vlapic->timer_last_update = vlapic->pt.last_plt_gtime + delta - period; + + HVM_DBG_LOG(DBG_LEVEL_VLAPIC, + "bus cycle is %uns, " + "initial count %u, period %"PRIu64"ns", + APIC_BUS_CYCLE_NS, + offset == APIC_TMICT + ? val : vlapic_get_reg(vlapic, APIC_TMICT), + period); + } + else + { + TRACE_0D(TRC_HVM_EMUL_LAPIC_STOP_TIMER); + destroy_periodic_time(&vlapic->pt); + /* From now, TMCCT should be 0 until TMICT is set. */ + vlapic->timer_last_update = 0; + } +} + + static void vlapic_reg_write(struct vcpu *v, unsigned int offset, uint32_t val) { @@ -733,13 +813,10 @@ static void vlapic_reg_write(struct vcpu *v, if ( (vlapic_get_reg(vlapic, offset) & APIC_TIMER_MODE_MASK) != (val & APIC_TIMER_MODE_MASK) ) { - TRACE_0D(TRC_HVM_EMUL_LAPIC_STOP_TIMER); - destroy_periodic_time(&vlapic->pt); - vlapic_set_reg(vlapic, APIC_TMICT, 0); - vlapic_set_reg(vlapic, APIC_TMCCT, 0); vlapic->hw.tdt_msr = 0; } vlapic->pt.irq = val & APIC_VECTOR_MASK; + vlapic_update_timer(vlapic, APIC_LVTT, val); /* fallthrough */ case APIC_LVTTHMR: /* LVT Thermal Monitor */ case APIC_LVTPC: /* LVT Performance Counter */ @@ -763,34 +840,10 @@ static void vlapic_reg_write(struct vcpu *v, case APIC_TMICT: { - uint64_t period; - if ( !vlapic_lvtt_oneshot(vlapic) && !vlapic_lvtt_period(vlapic) ) break; - + vlapic_update_timer(vlapic, APIC_TMICT, val); vlapic_set_reg(vlapic, APIC_TMICT, val); - if ( val == 0 ) - { - TRACE_0D(TRC_HVM_EMUL_LAPIC_STOP_TIMER); - destroy_periodic_time(&vlapic->pt); - break; - } - - period = (uint64_t)APIC_BUS_CYCLE_NS * val * vlapic->hw.timer_divisor; - TRACE_2_LONG_3D(TRC_HVM_EMUL_LAPIC_START_TIMER, TRC_PAR_LONG(period), - TRC_PAR_LONG(vlapic_lvtt_period(vlapic) ? period : 0LL), - vlapic->pt.irq); - create_periodic_time(current, &vlapic->pt, period, - vlapic_lvtt_period(vlapic) ? period : 0, - vlapic->pt.irq, - vlapic_lvtt_period(vlapic) ? vlapic_pt_cb : NULL, - &vlapic->timer_last_update); - vlapic->timer_last_update = vlapic->pt.last_plt_gtime; - - HVM_DBG_LOG(DBG_LEVEL_VLAPIC, - "bus cycle is %uns, " - "initial count %u, period %"PRIu64"ns", - APIC_BUS_CYCLE_NS, val, period); } break;