From patchwork Thu Mar 30 06:19:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9652969 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 63910602BD for ; Thu, 30 Mar 2017 06:22:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 537B528571 for ; Thu, 30 Mar 2017 06:22:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 46FE828574; Thu, 30 Mar 2017 06:22:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D44D32856C for ; Thu, 30 Mar 2017 06:22:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctTRU-0000t0-3h; Thu, 30 Mar 2017 06:20:20 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctTRT-0000sX-Gp for xen-devel@lists.xen.org; Thu, 30 Mar 2017 06:20:19 +0000 Received: from [85.158.137.68] by server-16.bemta-3.messagelabs.com id F6/8A-06437-2A3ACD85; Thu, 30 Mar 2017 06:20:18 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRWlGSWpSXmKPExsXS1tYhr7to8Z0 Ig30nuS2WfFzM4sDocXT3b6YAxijWzLyk/IoE1oxvkz6zF5ySrji17SFrA+NHsS5GTg4hgUqJ 3SfbmUBsCQFeiSPLZrBC2P4SuxoesXUxcgHV9DJKTN65EizBJqAvseLxQTBbREBa4trny4wgR cwCxxkl9u86xQKSEBYIlzi+ZzEjiM0ioCrR9eYjWAOvgI3EnGuTobbJS1y4ClHPKWArsfprOw vERTYSZ68dYpvAyLuAkWEVo3pxalFZapGupV5SUWZ6RkluYmaOrqGBsV5uanFxYnpqTmJSsV5 yfu4mRmA41DMwMO5gfP3T6RCjJAeTkijv5rl3IoT4kvJTKjMSizPii0pzUosPMcpwcChJ8Pos AsoJFqWmp1akZeYAAxMmLcHBoyTCexIkzVtckJhbnJkOkTrFqCglzusOkhAASWSU5sG1waLhE qOslDAvIwMDgxBPQWpRbmYJqvwrRnEORiVhXkmQKTyZeSVw018BLWYCWixucwtkcUkiQkqqgX GpdHoyZ+na9RHFnxU3ySQtiE7dYRa/LP5f2Ncj3/fPesb6Rbfr/TNFp+LluVPW+uS9FrIJP7R +86eNu/Silthts56jcuOFzQ0+20S7BEWt0EpGDRO55pPRE/ZVFLRPc3r9yO3p7ja3uacXSu04 ZMH+eM4vNb2FDk096ieWfZY+91Pizty0sEIlluKMREMt5qLiRAA3SumogQIAAA== X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-16.tower-31.messagelabs.com!1490854812!85204125!4 X-Originating-IP: [134.134.136.31] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 25452 invoked from network); 30 Mar 2017 06:20:17 -0000 Received: from mga06.intel.com (HELO mga06.intel.com) (134.134.136.31) by server-16.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 30 Mar 2017 06:20:17 -0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP; 29 Mar 2017 23:20:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,245,1486454400"; d="scan'208";a="241919468" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by fmsmga004.fm.intel.com with ESMTP; 29 Mar 2017 23:20:16 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Thu, 30 Mar 2017 14:19:57 +0800 Message-Id: <20170330062003.9119-4-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170330062003.9119-1-haozhong.zhang@intel.com> References: <20170330062003.9119-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Kevin Tian , Jun Nakajima , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH v3 3/9] x86/vmx: expose LMCE feature via guest MSR_IA32_FEATURE_CONTROL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then set LMCE and LOCK bits in guest MSR_IA32_FEATURE_CONTROL. Intel SDM requires those bits are set before SW can enable LMCE. Signed-off-by: Haozhong Zhang Reviewed-by: Jan Beulich Reviewed-by: Kevin Tian --- Cc: Jan Beulich Cc: Andrew Cooper Cc: Jun Nakajima Cc: Kevin Tian Changes in v3: * Rename vmce_support_lmce() to vmce_has_lmce(). * Add const to "curr" in vmx_msr_read_intercept(). --- xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ++++ xen/arch/x86/hvm/vmx/vmx.c | 9 +++++++++ xen/arch/x86/hvm/vmx/vvmx.c | 4 ---- xen/include/asm-x86/mce.h | 1 + 4 files changed, 14 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 3c57052..8528452 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -946,3 +946,7 @@ int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) return 1; } +bool vmce_has_lmce(const struct vcpu *v) +{ + return v->arch.vmce.mcg_cap & MCG_LMCE_P; +} diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index d201956..9ee1856 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include @@ -2745,6 +2746,8 @@ static int is_last_branch_msr(u32 ecx) static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content) { + const struct vcpu *curr = current; + HVM_DBG_LOG(DBG_LEVEL_MSR, "ecx=%#x", msr); switch ( msr ) @@ -2762,6 +2765,12 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content) __vmread(GUEST_IA32_DEBUGCTL, msr_content); break; case MSR_IA32_FEATURE_CONTROL: + *msr_content = IA32_FEATURE_CONTROL_LOCK; + if ( vmce_has_lmce(curr) ) + *msr_content |= IA32_FEATURE_CONTROL_LMCE_ON; + if ( nestedhvm_enabled(curr->domain) ) + *msr_content |= IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; + break; case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_VMFUNC: if ( !nvmx_msr_read_intercept(msr, msr_content) ) goto gp_fault; diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 09e4250..f41186d 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -2084,10 +2084,6 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) data = gen_vmx_msr(data, VMX_ENTRY_CTLS_DEFAULT1, host_data); break; - case MSR_IA32_FEATURE_CONTROL: - data = IA32_FEATURE_CONTROL_LOCK | - IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; - break; case MSR_IA32_VMX_VMCS_ENUM: /* The max index of VVMCS encoding is 0x1f. */ data = 0x1f << 1; diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h index 549bef3..56ad1f9 100644 --- a/xen/include/asm-x86/mce.h +++ b/xen/include/asm-x86/mce.h @@ -36,6 +36,7 @@ extern void vmce_init_vcpu(struct vcpu *); extern int vmce_restore_vcpu(struct vcpu *, const struct hvm_vmce_vcpu *); extern int vmce_wrmsr(uint32_t msr, uint64_t val); extern int vmce_rdmsr(uint32_t msr, uint64_t *val); +extern bool vmce_has_lmce(const struct vcpu *v); extern unsigned int nr_mce_banks;