From patchwork Tue May 30 14:05:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ross Lagerwall X-Patchwork-Id: 9754647 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3912660390 for ; Tue, 30 May 2017 14:07:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B5FB26E74 for ; Tue, 30 May 2017 14:07:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1FA952847B; Tue, 30 May 2017 14:07:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 72D1227F07 for ; Tue, 30 May 2017 14:07:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dFhlv-0000ib-GH; Tue, 30 May 2017 14:05:19 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dFhlt-0000iL-AU for xen-devel@lists.xenproject.org; Tue, 30 May 2017 14:05:17 +0000 Received: from [85.158.139.211] by server-4.bemta-5.messagelabs.com id EF/67-02181-C1C7D295; Tue, 30 May 2017 14:05:16 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRWlGSWpSXmKPExsXitHRDpK5EjW6 kQcMrc4vvWyYzOTB6HP5whSWAMYo1My8pvyKBNWPJ3sesBVP0K/qm9DE1MF5W6WLk5JAQ8JeY N3MRC4jNJmAgcevSd+YuRg4OEQEVidt7DboYuTiYBT4ySjw49oIVpEZYIERi88W77CA2i4Cqx IKWqcwgNq+AncTBtX/ZIGbKSSzdfh0sLiSgJvF2+RkWiBpBiZMzn4DZzAISEgdfvGCewMg9C0 lqFpLUAkamVYwaxalFZalFukYWeklFmekZJbmJmTm6hgamermpxcWJ6ak5iUnFesn5uZsYgcF Qz8DAuIOxb5XfIUZJDiYlUV5na91IIb6k/JTKjMTijPii0pzU4kOMMhwcShK8W6qAcoJFqemp FWmZOcCwhElLcPAoifCqg6R5iwsSc4sz0yFSpxh1OTasXv+FSYglLz8vVUqctwekSACkKKM0D 24ELEYuMcpKCfMyMjAwCPEUpBblZpagyr9iFOdgVBLmXQIyhSczrwRu0yugI5iAjti1QxvkiJ JEhJRUA2ObcupFmT+xFmeqdvmVsU8Wbjbb0cqivntu/ua87wapP5b/e6XOufPxpj/sEy3erW9 RCu4r/vzrbXrHnKAoEY7F7HLKLX/dTkj/Ud25QKQout25K61JmumTht7TqcdyP4XU68ULlFz+ 8FHH0/6t6WnH0icNa67W2CQkXm9i4MpddlzM+0apsRJLcUaioRZzUXEiAMD9qziMAgAA X-Env-Sender: prvs=316b4064f=ross.lagerwall@citrix.com X-Msg-Ref: server-5.tower-206.messagelabs.com!1496153110!99348604!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3038 invoked from network); 30 May 2017 14:05:12 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-5.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 30 May 2017 14:05:12 -0000 X-IronPort-AV: E=Sophos;i="5.38,418,1491264000"; d="scan'208";a="425880971" From: Ross Lagerwall To: Date: Tue, 30 May 2017 15:05:04 +0100 Message-ID: <20170530140504.22563-1-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.9.4 MIME-Version: 1.0 Cc: Sergey Dyasli , Kevin Tian , Jun Nakajima , Andrew Cooper , Ross Lagerwall , Jan Beulich Subject: [Xen-devel] [PATCH v2] x86/vmx: Fix vmentry failure because of invalid LER on Broadwell X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Occasionally, on certain Broadwell CPUs MSR_IA32_LASTINTTOIP has been observed to have the top three bits corrupted as though the MSR is using the LBR_FORMAT_EIP_FLAGS_TSX format. This is incorrect and causes a vmentry failure -- the MSR should contain an offset into the current code segment. This is assumed to be erratum BDF14. Workaround the issue by sign-extending into bits 48:63 for MSR_IA32_LASTINT{FROM,TO}IP. Signed-off-by: Ross Lagerwall Reviewed-by: Andrew Cooper , with one minor Reviewed-by: Kevin Tian --- Changes in v2: - Use a single check if fixup is needed. - Rename to include the erratum name/number. - Sign extend properly rather than just the top three bits. xen/arch/x86/hvm/vmx/vmx.c | 62 +++++++++++++++++++++++++++++++++++--- xen/include/asm-x86/hvm/vmx/vmcs.h | 2 +- xen/include/asm-x86/x86_64/page.h | 3 ++ 3 files changed, 62 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index c8ef18a..9e1179a 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2434,6 +2434,7 @@ static void pi_notification_interrupt(struct cpu_user_regs *regs) } static void __init lbr_tsx_fixup_check(void); +static void __init bdw_erratum_bdf14_fixup_check(void); const struct hvm_function_table * __init start_vmx(void) { @@ -2499,6 +2500,7 @@ const struct hvm_function_table * __init start_vmx(void) setup_vmcs_dump(); lbr_tsx_fixup_check(); + bdw_erratum_bdf14_fixup_check(); return &vmx_function_table; } @@ -2791,7 +2793,11 @@ enum #define LBR_FROM_SIGNEXT_2MSB ((1ULL << 59) | (1ULL << 60)) +#define FIXUP_LBR_TSX (1 << 0) +#define FIXUP_BDW_ERRATUM_BDF14 (1 << 1) + static bool __read_mostly lbr_tsx_fixup_needed; +static bool __read_mostly bdw_erratum_bdf14_fixup_needed; static uint32_t __read_mostly lbr_from_start; static uint32_t __read_mostly lbr_from_end; static uint32_t __read_mostly lbr_lastint_from; @@ -2828,6 +2834,13 @@ static void __init lbr_tsx_fixup_check(void) } } +static void __init bdw_erratum_bdf14_fixup_check(void) +{ + /* Broadwell E5-2600 v4 processors need to work around erratum BDF14. */ + if ( boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 79 ) + bdw_erratum_bdf14_fixup_needed = true; +} + static int is_last_branch_msr(u32 ecx) { const struct lbr_info *lbr = last_branch_msr_get(); @@ -3087,8 +3100,11 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) if ( (rc = vmx_add_guest_msr(lbr->base + i)) == 0 ) { vmx_disable_intercept_for_msr(v, lbr->base + i, MSR_TYPE_R | MSR_TYPE_W); - v->arch.hvm_vmx.lbr_tsx_fixup_enabled = - lbr_tsx_fixup_needed; + if ( lbr_tsx_fixup_needed ) + v->arch.hvm_vmx.lbr_fixup_enabled |= FIXUP_LBR_TSX; + if ( bdw_erratum_bdf14_fixup_needed ) + v->arch.hvm_vmx.lbr_fixup_enabled |= + FIXUP_BDW_ERRATUM_BDF14; } } @@ -4174,6 +4190,44 @@ static void lbr_tsx_fixup(void) msr->data |= ((LBR_FROM_SIGNEXT_2MSB & msr->data) << 2); } +static void sign_extend_msr(u32 msr, int type) +{ + struct vmx_msr_entry *entry; + + if ( (entry = vmx_find_msr(msr, type)) != NULL ) + { + if ( entry->data & VADDR_TOP_BIT ) + entry->data |= CANONICAL_MASK; + else + entry->data &= ~CANONICAL_MASK; + } +} + +static void bdw_erratum_bdf14_fixup(void) +{ + /* + * Occasionally, on certain Broadwell CPUs MSR_IA32_LASTINTTOIP has + * been observed to have the top three bits corrupted as though the + * MSR is using the LBR_FORMAT_EIP_FLAGS_TSX format. This is + * incorrect and causes a vmentry failure -- the MSR should contain + * an offset into the current code segment. This is assumed to be + * erratum BDF14. Fix up MSR_IA32_LASTINT{FROM,TO}IP by + * sign-extending into bits 48:63. + */ + sign_extend_msr(MSR_IA32_LASTINTFROMIP, VMX_GUEST_MSR); + sign_extend_msr(MSR_IA32_LASTINTTOIP, VMX_GUEST_MSR); +} + +static void lbr_fixup(void) +{ + struct vcpu *curr = current; + + if ( curr->arch.hvm_vmx.lbr_fixup_enabled & FIXUP_LBR_TSX ) + lbr_tsx_fixup(); + if ( curr->arch.hvm_vmx.lbr_fixup_enabled & FIXUP_BDW_ERRATUM_BDF14 ) + bdw_erratum_bdf14_fixup(); +} + void vmx_vmenter_helper(const struct cpu_user_regs *regs) { struct vcpu *curr = current; @@ -4230,8 +4284,8 @@ void vmx_vmenter_helper(const struct cpu_user_regs *regs) } out: - if ( unlikely(curr->arch.hvm_vmx.lbr_tsx_fixup_enabled) ) - lbr_tsx_fixup(); + if ( unlikely(curr->arch.hvm_vmx.lbr_fixup_enabled) ) + lbr_fixup(); HVMTRACE_ND(VMENTRY, 0, 1/*cycles*/, 0, 0, 0, 0, 0, 0, 0); diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h index 9507bd2..e3cdfdf 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -136,7 +136,7 @@ struct arch_vmx_struct { /* Are we emulating rather than VMENTERing? */ uint8_t vmx_emulate; - bool lbr_tsx_fixup_enabled; + uint8_t lbr_fixup_enabled; /* Bitmask of segments that we can't safely use in virtual 8086 mode */ uint16_t vm86_segment_mask; diff --git a/xen/include/asm-x86/x86_64/page.h b/xen/include/asm-x86/x86_64/page.h index 1a6cae6..d787724 100644 --- a/xen/include/asm-x86/x86_64/page.h +++ b/xen/include/asm-x86/x86_64/page.h @@ -28,6 +28,9 @@ #define PADDR_MASK ((1UL << PADDR_BITS)-1) #define VADDR_MASK ((1UL << VADDR_BITS)-1) +#define VADDR_TOP_BIT (1UL << (VADDR_BITS - 1)) +#define CANONICAL_MASK (~0UL & ~((1UL << VADDR_BITS) - 1)) + #define is_canonical_address(x) (((long)(x) >> 47) == ((long)(x) >> 63)) #ifndef __ASSEMBLY__