From patchwork Thu Jun 15 20:30:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 9790171 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ECB4D60325 for ; Thu, 15 Jun 2017 20:33:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE7B527FB6 for ; Thu, 15 Jun 2017 20:33:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D269628517; Thu, 15 Jun 2017 20:33:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5DE8E27FB6 for ; Thu, 15 Jun 2017 20:33:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dLbQ8-0001WQ-U5; Thu, 15 Jun 2017 20:31:12 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dLbQ7-0001W4-Av for xen-devel@lists.xen.org; Thu, 15 Jun 2017 20:31:11 +0000 Received: from [85.158.143.35] by server-4.bemta-6.messagelabs.com id 3C/BA-02956-E8EE2495; Thu, 15 Jun 2017 20:31:10 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTbfvnVO kwdaJrBZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8atRdvZClqUKlrefmNpYJwv2cXIySEksJlR Ytc0+S5GLiD7NKPE181fGEESbAKaEnc+f2ICsUUEpCWufb4MFmcWiJJovr2UHcQWFrCV+Df7M BuIzSKgKnFtx0UWEJtXwFxiz8mNzCC2hIC8xK62i6wgNqeAhcTmV81MEIvNJV486GSfwMi9gJ FhFaN6cWpRWWqRrpFeUlFmekZJbmJmjq6hgZlebmpxcWJ6ak5iUrFecn7uJkagdxmAYAfjsr9 OhxglOZiURHn55ZwihfiS8lMqMxKLM+KLSnNSiw8xynBwKEnwdr0FygkWpaanVqRl5gDDDCYt wcGjJMLL/hgozVtckJhbnJkOkTrFqCglzjsdpE8AJJFRmgfXBgvtS4yyUsK8jECHCPEUpBblZ pagyr9iFOdgVBLm5QeZwpOZVwI3/RXQYiagxUEXHEAWlyQipKQaGA11NhZtqtvifnR7Yp2TfO eVgC/za91UWs5y2+ld973S+4O3fqmVwE3D3VsUGktTC7lnZyy9/MZh0u24jlMW79T+KXsnl2+ /MyclgX+Z/faa2qdHG0wk7z9UDGBi3ft8o+Hdxafm8a3+mdP2Y7bWtf9/DhUFKp/1Np7f1vNd 3dvpmFH99fQpD5RYijMSDbWYi4oTAeL7BGNoAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-12.tower-21.messagelabs.com!1497558669!74104236!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 52654 invoked from network); 15 Jun 2017 20:31:09 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-12.tower-21.messagelabs.com with SMTP; 15 Jun 2017 20:31:09 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C54615BF; Thu, 15 Jun 2017 13:31:09 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 75F833F3E1; Thu, 15 Jun 2017 13:31:08 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Jun 2017 21:30:57 +0100 Message-Id: <20170615203057.755-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170615203057.755-1-julien.grall@arm.com> References: <20170615203057.755-1-julien.grall@arm.com> Cc: proskurin@sec.in.tum.de, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 2/2] xen/arm: lpae: Fix comments coding style X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Also adding one missing full stop. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/include/asm-arm/lpae.h | 45 ++++++++++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 15 deletions(-) diff --git a/xen/include/asm-arm/lpae.h b/xen/include/asm-arm/lpae.h index 1e6a68926e..6244240ca0 100644 --- a/xen/include/asm-arm/lpae.h +++ b/xen/include/asm-arm/lpae.h @@ -3,10 +3,12 @@ #ifndef __ASSEMBLY__ -/* WARNING! Unlike the Intel pagetable code, where l1 is the lowest +/* + * WARNING! Unlike the Intel pagetable code, where l1 is the lowest * level and l4 is the root of the trie, the ARM pagetables follow ARM's * documentation: the levels are called first, second &c in the order - * that the MMU walks them (i.e. "first" is the root of the trie). */ + * that the MMU walks them (i.e. "first" is the root of the trie). + */ /****************************************************************************** * ARMv7-A LPAE pagetables: 3-level trie, mapping 40-bit input to @@ -17,15 +19,18 @@ * different place from those in leaf nodes seems to be to allow linear * pagetable tricks. If we're not doing that then the set of permission * bits that's not in use in a given node type can be used as - * extra software-defined bits. */ + * extra software-defined bits. + */ typedef struct __packed { /* These are used in all kinds of entry. */ unsigned long valid:1; /* Valid mapping */ unsigned long table:1; /* == 1 in 4k map entries too */ - /* These ten bits are only used in Block entries and are ignored - * in Table entries. */ + /* + * These ten bits are only used in Block entries and are ignored + * in Table entries. + */ unsigned long ai:3; /* Attribute Index */ unsigned long ns:1; /* Not-Secure */ unsigned long user:1; /* User-visible */ @@ -38,30 +43,38 @@ typedef struct __packed { unsigned long long base:36; /* Base address of block or next table */ unsigned long sbz:4; /* Must be zero */ - /* These seven bits are only used in Block entries and are ignored - * in Table entries. */ + /* + * These seven bits are only used in Block entries and are ignored + * in Table entries. + */ unsigned long contig:1; /* In a block of 16 contiguous entries */ unsigned long pxn:1; /* Privileged-XN */ unsigned long xn:1; /* eXecute-Never */ unsigned long avail:4; /* Ignored by hardware */ - /* These 5 bits are only used in Table entries and are ignored in - * Block entries */ + /* + * These 5 bits are only used in Table entries and are ignored in + * Block entries. + */ unsigned long pxnt:1; /* Privileged-XN */ unsigned long xnt:1; /* eXecute-Never */ unsigned long apt:2; /* Access Permissions */ unsigned long nst:1; /* Not-Secure */ } lpae_pt_t; -/* The p2m tables have almost the same layout, but some of the permission - * and cache-control bits are laid out differently (or missing) */ +/* + * The p2m tables have almost the same layout, but some of the permission + * and cache-control bits are laid out differently (or missing). + */ typedef struct __packed { /* These are used in all kinds of entry. */ unsigned long valid:1; /* Valid mapping */ unsigned long table:1; /* == 1 in 4k map entries too */ - /* These ten bits are only used in Block entries and are ignored - * in Table entries. */ + /* + * These ten bits are only used in Block entries and are ignored + * in Table entries. + */ unsigned long mattr:4; /* Memory Attributes */ unsigned long read:1; /* Read access */ unsigned long write:1; /* Write access */ @@ -73,8 +86,10 @@ typedef struct __packed { unsigned long long base:36; /* Base address of block or next table */ unsigned long sbz3:4; - /* These seven bits are only used in Block entries and are ignored - * in Table entries. */ + /* + * These seven bits are only used in Block entries and are ignored + * in Table entries. + */ unsigned long contig:1; /* In a block of 16 contiguous entries */ unsigned long sbz2:1; unsigned long xn:1; /* eXecute-Never */