From patchwork Mon Jun 26 09:16:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9808913 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C4CE360209 for ; Mon, 26 Jun 2017 09:19:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD80328161 for ; Mon, 26 Jun 2017 09:19:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C013428437; Mon, 26 Jun 2017 09:19:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0C25A2847C for ; Mon, 26 Jun 2017 09:19:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dPQ8h-0002jr-FU; Mon, 26 Jun 2017 09:16:59 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dPQ8g-0002jV-PV for xen-devel@lists.xen.org; Mon, 26 Jun 2017 09:16:58 +0000 Received: from [85.158.143.35] by server-2.bemta-6.messagelabs.com id 2D/92-03058-A01D0595; Mon, 26 Jun 2017 09:16:58 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPLMWRWlGSWpSXmKPExsVywNwkVpfzYkC kwcVTqhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bClXdYCk5IVxxuNGlg/CnWxcjFISQwjVHi +qNvzF2MnBwSArwSR5bNYIWw/SW+fPjEClHUyyjR8WEFE0iCTUBfYsXjg2BFIgLSEtc+X2YEK WIWOM4osX/XKRaQhLBApMTd2VPAprIIqErcXP6GHcTmFbCV2HfsKTvEBnmJXW0XwQZxCthJvP h7ACwuBFQz4dcKxgmMvAsYGVYxahSnFpWlFukaWuglFWWmZ5TkJmbm6BoamOnlphYXJ6an5iQ mFesl5+duYgQGBAMQ7GC8uTHgEKMkB5OSKG+jv3+kEF9SfkplRmJxRnxRaU5q8SFGGQ4OJQne c+cDIoUEi1LTUyvSMnOAoQmTluDgURLhvXAWKM1bXJCYW5yZDpE6xagoJc47C6RPACSRUZoH1 waLh0uMslLCvIxAhwjxFKQW5WaWoMq/YhTnYFQS5m0HmcKTmVcCN/0V0GImoMUs88AWlyQipK QaGFfs0VjqkiWj0L+s/3/i5vxloixMpcJl76ZPErObaKjNXlz6hc3Nf/3bRseIy9M71u1hLtD QvjzDlWHr+sfKi6RPSF7+cVqk84zzdfsZf2rWHJfMrv4U//jGjRTepv+pQUyaKXGy7NKn/8g+ CLjSeU/iWfN6LclS12lLjpyT1Dx11UJaLPdQgxJLcUaioRZzUXEiAJWq1rWCAgAA X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-9.tower-21.messagelabs.com!1498468609!75505562!5 X-Originating-IP: [192.55.52.93] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjkzID0+IDMyNDY2NQ==\n X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 64978 invoked from network); 26 Jun 2017 09:16:57 -0000 Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by server-9.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 26 Jun 2017 09:16:57 -0000 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2017 02:16:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,395,1493708400"; d="scan'208";a="985229974" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.142]) by orsmga003.jf.intel.com with ESMTP; 26 Jun 2017 02:16:55 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Mon, 26 Jun 2017 17:16:19 +0800 Message-Id: <20170626091625.19655-6-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170626091625.19655-1-haozhong.zhang@intel.com> References: <20170626091625.19655-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Kevin Tian , Jun Nakajima , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH v4 05/11] x86/vmx: expose LMCE feature via guest MSR_IA32_FEATURE_CONTROL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then set LMCE and LOCK bits in guest MSR_IA32_FEATURE_CONTROL. Intel SDM requires those bits are set before SW can enable LMCE. Signed-off-by: Haozhong Zhang Reviewed-by: Kevin Tian Reviewed-by: Jan Beulich --- Cc: Jan Beulich Cc: Andrew Cooper Cc: Jun Nakajima Cc: Kevin Tian --- xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ++++ xen/arch/x86/hvm/vmx/vmx.c | 9 +++++++++ xen/arch/x86/hvm/vmx/vvmx.c | 4 ---- xen/include/asm-x86/mce.h | 1 + 4 files changed, 14 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 020b02deff..5cb49ca697 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -946,3 +946,7 @@ int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) return 1; } +bool vmce_has_lmce(const struct vcpu *v) +{ + return v->arch.vmce.mcg_cap & MCG_LMCE_P; +} diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index c53b24955a..6a193ef9d4 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include @@ -2856,6 +2857,8 @@ static int is_last_branch_msr(u32 ecx) static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content) { + const struct vcpu *curr = current; + HVM_DBG_LOG(DBG_LEVEL_MSR, "ecx=%#x", msr); switch ( msr ) @@ -2873,6 +2876,12 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content) __vmread(GUEST_IA32_DEBUGCTL, msr_content); break; case MSR_IA32_FEATURE_CONTROL: + *msr_content = IA32_FEATURE_CONTROL_LOCK; + if ( vmce_has_lmce(curr) ) + *msr_content |= IA32_FEATURE_CONTROL_LMCE_ON; + if ( nestedhvm_enabled(curr->domain) ) + *msr_content |= IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; + break; case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_VMFUNC: if ( !nvmx_msr_read_intercept(msr, msr_content) ) goto gp_fault; diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 3560faec6d..f451935ea6 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -2084,10 +2084,6 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) data = gen_vmx_msr(data, VMX_ENTRY_CTLS_DEFAULT1, host_data); break; - case MSR_IA32_FEATURE_CONTROL: - data = IA32_FEATURE_CONTROL_LOCK | - IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; - break; case MSR_IA32_VMX_VMCS_ENUM: /* The max index of VVMCS encoding is 0x1f. */ data = 0x1f << 1; diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h index 549bef3ebe..56ad1f92dd 100644 --- a/xen/include/asm-x86/mce.h +++ b/xen/include/asm-x86/mce.h @@ -36,6 +36,7 @@ extern void vmce_init_vcpu(struct vcpu *); extern int vmce_restore_vcpu(struct vcpu *, const struct hvm_vmce_vcpu *); extern int vmce_wrmsr(uint32_t msr, uint64_t val); extern int vmce_rdmsr(uint32_t msr, uint64_t *val); +extern bool vmce_has_lmce(const struct vcpu *v); extern unsigned int nr_mce_banks;