From patchwork Mon Jun 26 10:44:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Dyasli X-Patchwork-Id: 9809111 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 92FA260209 for ; Mon, 26 Jun 2017 10:47:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 99430223A6 for ; Mon, 26 Jun 2017 10:47:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8DD932785D; Mon, 26 Jun 2017 10:47:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0ACE0223A6 for ; Mon, 26 Jun 2017 10:47:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dPRVZ-00028i-QH; Mon, 26 Jun 2017 10:44:41 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dPRVZ-00028K-0y for xen-devel@lists.xen.org; Mon, 26 Jun 2017 10:44:41 +0000 Received: from [85.158.143.35] by server-4.bemta-6.messagelabs.com id 0E/B9-02956-895E0595; Mon, 26 Jun 2017 10:44:40 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeJIrShJLcpLzFFi42JxWrrBXnf604B Ig3MXLC2WfFzM4sDocXT3b6YAxijWzLyk/IoE1oxFR1cyFxyyrvj1bw5jA+NMnS5GTg4JAX+J F20XWUFsNgE9iY2zXzGB2CICshKru+awdzFycTALHGGUmLrqCJDDwSEsYCwx77wdSA2LgKrE8 +X9YL28ArYSk1vmM0LMlJfYBTWTU8BOYu6C0ywgthBQTdPTRWwQtqrE6xe7WCB6BSVOznwCZj MLSEgcfPGCeQIj7ywkqVlIUgsYmVYxqhenFpWlFula6CUVZaZnlOQmZuboGhqY6eWmFhcnpqf mJCYV6yXn525iBIYOAxDsYJx92f8QoyQHk5IoL8eTgEghvqT8lMqMxOKM+KLSnNTiQ4wyHBxK EryaIDnBotT01Iq0zBxgEMOkJTh4lER4jz4ESvMWFyTmFmemQ6ROMSpKifO6gPQJgCQySvPg2 mCRc4lRVkqYlxHoECGegtSi3MwSVPlXjOIcjErCvLkgU3gy80rgpr8CWswEtJhlHtjikkSElF QDo4J3zZK1/+b+XeO4NE7kSWlMTB/fck+T/5W7Szhn7o25df6g1oVrTYWmce2H0jeFGj6J8TM KjYllmyB1aW5do830xrMODWpH+Bdbeaa9b32zbs9e3ZdrVLVXVH5/kv3hTmnOTmHtf1LZNUUS 27qbhZLDv56+xnz2jY/aR8sW27Xpco8/ZNRsVGIpzkg01GIuKk4EAD/rnlWXAgAA X-Env-Sender: prvs=343936acc=sergey.dyasli@citrix.com X-Msg-Ref: server-11.tower-21.messagelabs.com!1498473878!75551093!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 59996 invoked from network); 26 Jun 2017 10:44:39 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-11.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 26 Jun 2017 10:44:39 -0000 X-IronPort-AV: E=Sophos;i="5.39,395,1493683200"; d="scan'208";a="437812349" From: Sergey Dyasli To: Date: Mon, 26 Jun 2017 11:44:31 +0100 Message-ID: <20170626104435.25508-3-sergey.dyasli@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170626104435.25508-1-sergey.dyasli@citrix.com> References: <20170626104435.25508-1-sergey.dyasli@citrix.com> MIME-Version: 1.0 Cc: Andrew Cooper , Kevin Tian , Jan Beulich , Jun Nakajima , Sergey Dyasli Subject: [Xen-devel] [PATCH v1 2/6] vmx: add raw_vmx_msr_policy X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add calculate_raw_policy() which fills raw_vmx_msr_policy (the actual contents of H/W VMX MSRs) on the boot CPU. On secondary CPUs, this function checks that contents of VMX MSRs match the boot CPU's contents. Remove lesser version of same-contents-check from vmx_init_vmcs_config(). Signed-off-by: Sergey Dyasli --- xen/arch/x86/hvm/vmx/vmcs.c | 130 +++++++++++++++++++++---------------- xen/arch/x86/hvm/vmx/vmx.c | 4 ++ xen/include/asm-x86/hvm/vmx/vmcs.h | 2 + 3 files changed, 79 insertions(+), 57 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index e6ea197230..00fbc0ccb8 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -144,6 +144,8 @@ static void __init vmx_display_features(void) printk(" - none\n"); } +struct vmx_msr_policy __read_mostly raw_vmx_msr_policy; + bool vmx_msr_available(struct vmx_msr_policy *p, uint32_t msr) { if ( msr < MSR_IA32_VMX_BASIC || msr > MSR_IA32_VMX_VMFUNC ) @@ -152,6 +154,74 @@ bool vmx_msr_available(struct vmx_msr_policy *p, uint32_t msr) return p->available & (1u << (msr - MSR_IA32_VMX_BASIC)); } +int calculate_raw_policy(bool bsp) +{ + struct vmx_msr_policy policy; + struct vmx_msr_policy *p = &policy; + int msr; + + /* Raw policy is filled only on boot CPU */ + if ( bsp ) + p = &raw_vmx_msr_policy; + else + memset(&policy, 0, sizeof(policy)); + + p->available = 0x7ff; + for ( msr = MSR_IA32_VMX_BASIC; msr <= MSR_IA32_VMX_VMCS_ENUM; msr++ ) + rdmsrl(msr, p->msr[msr - MSR_IA32_VMX_BASIC]); + + if ( p->basic.default1_zero ) + { + p->available |= 0x1e000; + for ( msr = MSR_IA32_VMX_TRUE_PINBASED_CTLS; + msr <= MSR_IA32_VMX_TRUE_ENTRY_CTLS; msr++ ) + rdmsrl(msr, p->msr[msr - MSR_IA32_VMX_BASIC]); + } + + if ( p->procbased_ctls.allowed_1.activate_secondary_controls ) + { + p->available |= 0x800; + msr = MSR_IA32_VMX_PROCBASED_CTLS2; + rdmsrl(msr, p->msr[msr - MSR_IA32_VMX_BASIC]); + + if ( p->procbased_ctls2.allowed_1.enable_ept || + p->procbased_ctls2.allowed_1.enable_vpid ) + { + p->available |= 0x1000; + msr = MSR_IA32_VMX_EPT_VPID_CAP; + rdmsrl(msr, p->msr[msr - MSR_IA32_VMX_BASIC]); + } + + if ( p->procbased_ctls2.allowed_1.enable_vm_functions ) + { + p->available |= 0x20000; + msr = MSR_IA32_VMX_VMFUNC; + rdmsrl(msr, p->msr[msr - MSR_IA32_VMX_BASIC]); + } + } + + /* Check that secondary CPUs have exactly the same bits in VMX MSRs */ + if ( !bsp && memcmp(p, &raw_vmx_msr_policy, sizeof(*p)) != 0 ) + { + for ( msr = MSR_IA32_VMX_BASIC; msr <= MSR_IA32_VMX_VMFUNC; msr++ ) + { + if ( p->msr[msr - MSR_IA32_VMX_BASIC] != + raw_vmx_msr_policy.msr[msr - MSR_IA32_VMX_BASIC] ) + { + printk("VMX msr %#x: saw 0x%016"PRIx64" expected 0x%016"PRIx64 + "\n", msr, p->msr[msr - MSR_IA32_VMX_BASIC], + raw_vmx_msr_policy.msr[msr - MSR_IA32_VMX_BASIC]); + } + } + + printk("VMX: Capabilities fatally differ between CPU%d and boot CPU\n", + smp_processor_id()); + return -EINVAL; + } + + return 0; +} + static u32 adjust_vmx_controls( const char *name, u32 ctl_min, u32 ctl_opt, u32 msr, bool_t *mismatch) { @@ -173,13 +243,6 @@ static u32 adjust_vmx_controls( return ctl; } -static bool_t cap_check(const char *name, u32 expected, u32 saw) -{ - if ( saw != expected ) - printk("VMX %s: saw %#x expected %#x\n", name, saw, expected); - return saw != expected; -} - static int vmx_init_vmcs_config(void) { u32 vmx_basic_msr_low, vmx_basic_msr_high, min, opt; @@ -412,56 +475,6 @@ static int vmx_init_vmcs_config(void) return -EINVAL; } } - else - { - /* Globals are already initialised: re-check them. */ - mismatch |= cap_check( - "VMCS revision ID", - vmcs_revision_id, vmx_basic_msr_low & VMX_BASIC_REVISION_MASK); - mismatch |= cap_check( - "Pin-Based Exec Control", - vmx_pin_based_exec_control, _vmx_pin_based_exec_control); - mismatch |= cap_check( - "CPU-Based Exec Control", - vmx_cpu_based_exec_control, _vmx_cpu_based_exec_control); - mismatch |= cap_check( - "Secondary Exec Control", - vmx_secondary_exec_control, _vmx_secondary_exec_control); - mismatch |= cap_check( - "VMExit Control", - vmx_vmexit_control, _vmx_vmexit_control); - mismatch |= cap_check( - "VMEntry Control", - vmx_vmentry_control, _vmx_vmentry_control); - mismatch |= cap_check( - "EPT and VPID Capability", - vmx_ept_vpid_cap, _vmx_ept_vpid_cap); - mismatch |= cap_check( - "VMFUNC Capability", - vmx_vmfunc, _vmx_vmfunc); - if ( cpu_has_vmx_ins_outs_instr_info != - !!(vmx_basic_msr_high & (VMX_BASIC_INS_OUT_INFO >> 32)) ) - { - printk("VMX INS/OUTS Instruction Info: saw %d expected %d\n", - !!(vmx_basic_msr_high & (VMX_BASIC_INS_OUT_INFO >> 32)), - cpu_has_vmx_ins_outs_instr_info); - mismatch = 1; - } - if ( (vmx_basic_msr_high & (VMX_BASIC_VMCS_SIZE_MASK >> 32)) != - ((vmx_basic_msr & VMX_BASIC_VMCS_SIZE_MASK) >> 32) ) - { - printk("VMX: CPU%d unexpected VMCS size %Lu\n", - smp_processor_id(), - vmx_basic_msr_high & (VMX_BASIC_VMCS_SIZE_MASK >> 32)); - mismatch = 1; - } - if ( mismatch ) - { - printk("VMX: Capabilities fatally differ between CPU%d and CPU0\n", - smp_processor_id()); - return -EINVAL; - } - } /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ if ( vmx_basic_msr_high & (VMX_BASIC_32BIT_ADDRESSES >> 32) ) @@ -611,6 +624,9 @@ int vmx_cpu_up(void) BUG_ON(!(read_cr4() & X86_CR4_VMXE)); + if ( (rc = calculate_raw_policy(false)) != 0 ) + return rc; + /* * Ensure the current processor operating mode meets * the requred CRO fixed bits in VMX operation. diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index c53b24955a..f344d6a5ea 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2432,6 +2432,8 @@ static void pi_notification_interrupt(struct cpu_user_regs *regs) raise_softirq(VCPU_KICK_SOFTIRQ); } +int calculate_raw_policy(bool bsp); + static void __init lbr_tsx_fixup_check(void); static void __init bdw_erratum_bdf14_fixup_check(void); @@ -2439,6 +2441,8 @@ const struct hvm_function_table * __init start_vmx(void) { set_in_cr4(X86_CR4_VMXE); + calculate_raw_policy(true); + if ( vmx_cpu_up() ) { printk("VMX: failed to initialise.\n"); diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h index fca1e62e4c..8b97f85c46 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -904,6 +904,8 @@ struct vmx_msr_policy }; }; +extern struct vmx_msr_policy raw_vmx_msr_policy; + bool vmx_msr_available(struct vmx_msr_policy *p, uint32_t msr); #endif /* ASM_X86_HVM_VMX_VMCS_H__ */