From patchwork Mon Jun 26 10:44:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Dyasli X-Patchwork-Id: 9809113 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8180160209 for ; Mon, 26 Jun 2017 10:47:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 85B22223A6 for ; Mon, 26 Jun 2017 10:47:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7A5DB2785D; Mon, 26 Jun 2017 10:47:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 745F4223A6 for ; Mon, 26 Jun 2017 10:47:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dPRVc-0002Ae-7D; Mon, 26 Jun 2017 10:44:44 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dPRVb-00029E-2r for xen-devel@lists.xen.org; Mon, 26 Jun 2017 10:44:43 +0000 Received: from [193.109.254.147] by server-7.bemta-6.messagelabs.com id C8/4C-03620-A95E0595; Mon, 26 Jun 2017 10:44:42 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEIsWRWlGSWpSXmKPExsXitHSDve7MpwG RBkf2Glks+biYxYHR4+ju30wBjFGsmXlJ+RUJrBnTli5mLJg9g7HiyYYe9gbG/6VdjJwcEgL+ Elu37WYDsdkE9CQ2zn7FBGKLCMhKrO6aw97FyMXBLHCEUWLqqiPsIAlhAQ+J01PvsIDYLAKqE tOaNgHFOTh4BWwlbtzJgJgpL7Gr7SIriM0pYCcxd8FpsHIhoJKmp4vYIGxVidcvdoHFeQUEJU 7OfAJmMwtISBx88YJ5AiPvLCSpWUhSCxiZVjFqFKcWlaUW6Rqa6iUVZaZnlOQmZuboGhqY6eW mFhcnpqfmJCYV6yXn525iBIYPAxDsYPy2LOAQoyQHk5IoL8eTgEghvqT8lMqMxOKM+KLSnNTi Q4wyHBxKEryaIDnBotT01Iq0zBxgIMOkJTh4lER4jz4ESvMWFyTmFmemQ6ROMepybFi9/guTE Etefl6qlDivC8gMAZCijNI8uBGwqLrEKCslzMsIdJQQT0FqUW5mCar8K0ZxDkYlYV4DkCk8mX klcJteAR3BBHQEyzywI0oSEVJSDYyxv1Y6LXLYOdNbdnd9k/SeadukJQU4Xy1dUsNpml273dr uWGLh5Wuud5exub4o2lq2ZrpxaL/zQWVV9+3fIn5P33uBM0TPQbjonFjY4fIjRnnflmqGe4jm 6TJbMa39xbFiNtv29675X65Yfs07GbJ3cx9DhEOSfZPM8eUL9vi3V4R1Sbd/W6PEUpyRaKjFX FScCAD8dFd5pQIAAA== X-Env-Sender: prvs=343936acc=sergey.dyasli@citrix.com X-Msg-Ref: server-16.tower-27.messagelabs.com!1498473880!109128724!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 41915 invoked from network); 26 Jun 2017 10:44:41 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-16.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 26 Jun 2017 10:44:41 -0000 X-IronPort-AV: E=Sophos;i="5.39,395,1493683200"; d="scan'208";a="437812352" From: Sergey Dyasli To: Date: Mon, 26 Jun 2017 11:44:35 +0100 Message-ID: <20170626104435.25508-7-sergey.dyasli@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170626104435.25508-1-sergey.dyasli@citrix.com> References: <20170626104435.25508-1-sergey.dyasli@citrix.com> MIME-Version: 1.0 Cc: Andrew Cooper , Kevin Tian , Jan Beulich , Jun Nakajima , Sergey Dyasli Subject: [Xen-devel] [DEBUG PATCH 6/6] vmx: print H/W VMX MSRs values during startup X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This is a debug patch I used when developing this series. It's not intended for merging, I post it because it might be useful to someone. Signed-off-by: Sergey Dyasli --- xen/arch/x86/hvm/vmx/vmcs.c | 405 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 405 insertions(+) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index da6ddf52f1..b142f29560 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -154,6 +154,408 @@ bool vmx_msr_available(struct vmx_msr_policy *p, uint32_t msr) return p->available & (1u << (msr - MSR_IA32_VMX_BASIC)); } +static char *vmx_msr_bit_status(u32 mask, u32 all_0, u32 all_1) +{ + if ( (all_0 & mask) && (all_1 & mask) ) + return "1"; + if ( !(all_0 & mask) && !(all_1 & mask) ) + return "0"; + + return "0/1"; +} + +static char *btoa(uint32_t val) +{ + return val ? "yes" : "no"; +} + +static void print_vmx_basic_msr(struct vmx_msr_policy *p) +{ + printk("%-33s %#018lx\n", "MSR_IA32_VMX_BASIC", p->basic.raw); + printk(" %-31s %#x\n", "VMCS revision:", p->basic.vmcs_revision_id); + printk(" %-31s %d\n", "VMCS/VMXON region size:", + p->basic.vmcs_region_size); + printk(" %-31s %s\n", "32-bit phys addr limit:", + btoa(p->basic.addresses_32bit)); + printk(" %-31s %s\n", "Dual monitor mode:", btoa(p->basic.dual_monitor)); + printk(" %-31s %d ", "VMCS memory type:", p->basic.memory_type); + switch ( p->basic.memory_type ) + { + case MTRR_TYPE_UNCACHABLE: + printk("(Uncacheable)\n"); + break; + case MTRR_TYPE_WRBACK: + printk("(Write Back)\n"); + break; + default: + printk("(Unrecognized)\n"); + break; + } + printk(" %-31s %s\n", "Report INS/OUTS VM exits:", + btoa(p->basic.ins_out_info)); + printk(" %-31s %s\n", "Default1 CTLS clearable:", + btoa(p->basic.default1_zero)); +} + +static void print_vmx_msr_pinbased_bits(u32 all_0, u32 all_1) +{ + printk(" %-31s %s\n", "External-interrupt exiting:", + vmx_msr_bit_status(PIN_BASED_EXT_INTR_MASK, all_0, all_1)); + printk(" %-31s %s\n", "NMI exiting:", + vmx_msr_bit_status(PIN_BASED_NMI_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "Virtual NMIs:", + vmx_msr_bit_status(PIN_BASED_VIRTUAL_NMIS, all_0, all_1)); + printk(" %-31s %s\n", "VMX-preemption timer:", + vmx_msr_bit_status(PIN_BASED_PREEMPT_TIMER, all_0, all_1)); + printk(" %-31s %s\n", "Posted interrupts:", + vmx_msr_bit_status(PIN_BASED_POSTED_INTERRUPT, all_0, all_1)); +} + +static void print_vmx_msr_procbased_bits(u32 all_0, u32 all_1) +{ + printk(" %-31s %s\n", "Interrupt-window exiting:", + vmx_msr_bit_status(CPU_BASED_VIRTUAL_INTR_PENDING, all_0, all_1)); + printk(" %-31s %s\n", "Use TSC offsetting:", + vmx_msr_bit_status(CPU_BASED_USE_TSC_OFFSETING, all_0, all_1)); + printk(" %-31s %s\n", "HLT exiting:", + vmx_msr_bit_status(CPU_BASED_HLT_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "INVLPG exiting:", + vmx_msr_bit_status(CPU_BASED_INVLPG_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "MWAIT exiting:", + vmx_msr_bit_status(CPU_BASED_MWAIT_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "RDPMC exiting:", + vmx_msr_bit_status(CPU_BASED_RDPMC_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "RDTSC exiting:", + vmx_msr_bit_status(CPU_BASED_RDTSC_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "CR3-load exiting:", + vmx_msr_bit_status(CPU_BASED_CR3_LOAD_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "CR3-store exiting:", + vmx_msr_bit_status(CPU_BASED_CR3_STORE_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "CR8-load exiting:", + vmx_msr_bit_status(CPU_BASED_CR8_LOAD_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "CR8-store exiting:", + vmx_msr_bit_status(CPU_BASED_CR8_STORE_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "Use TPR shadow:", + vmx_msr_bit_status(CPU_BASED_TPR_SHADOW, all_0, all_1)); + printk(" %-31s %s\n", "NMI-window exiting:", + vmx_msr_bit_status(CPU_BASED_VIRTUAL_NMI_PENDING, all_0, all_1)); + printk(" %-31s %s\n", "MOV-DR exiting:", + vmx_msr_bit_status(CPU_BASED_MOV_DR_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "Unconditional I/O exiting:", + vmx_msr_bit_status(CPU_BASED_UNCOND_IO_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "Use I/O bitmaps:", + vmx_msr_bit_status(CPU_BASED_ACTIVATE_IO_BITMAP, all_0, all_1)); + printk(" %-31s %s\n", "Monitor trap flag:", + vmx_msr_bit_status(CPU_BASED_MONITOR_TRAP_FLAG, all_0, all_1)); + printk(" %-31s %s\n", "Use MSR bitmaps:", + vmx_msr_bit_status(CPU_BASED_ACTIVATE_MSR_BITMAP, all_0, all_1)); + printk(" %-31s %s\n", "MONITOR exiting:", + vmx_msr_bit_status(CPU_BASED_MONITOR_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "PAUSE exiting:", + vmx_msr_bit_status(CPU_BASED_PAUSE_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "Activate secondary controls:", + vmx_msr_bit_status(CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, + all_0, all_1)); +} + +static void print_vmx_msr_exit_bits(u32 all_0, u32 all_1) +{ + printk(" %-31s %s\n", "Save debug controls:", + vmx_msr_bit_status(VM_EXIT_SAVE_DEBUG_CNTRLS, all_0, all_1)); + printk(" %-31s %s\n", "Host address-space size:", + vmx_msr_bit_status(VM_EXIT_IA32E_MODE, all_0, all_1)); + printk(" %-31s %s\n", "Load IA32_PERF_GLOBAL_CTRL:", + vmx_msr_bit_status(VM_EXIT_LOAD_PERF_GLOBAL_CTRL, all_0, all_1)); + printk(" %-31s %s\n", "Acknowledge interrupt on exit:", + vmx_msr_bit_status(VM_EXIT_ACK_INTR_ON_EXIT, all_0, all_1)); + printk(" %-31s %s\n", "Save IA32_PAT:", + vmx_msr_bit_status(VM_EXIT_SAVE_GUEST_PAT, all_0, all_1)); + printk(" %-31s %s\n", "Load IA32_PAT:", + vmx_msr_bit_status(VM_EXIT_LOAD_HOST_PAT, all_0, all_1)); + printk(" %-31s %s\n", "Save IA32_EFER:", + vmx_msr_bit_status(VM_EXIT_SAVE_GUEST_EFER, all_0, all_1)); + printk(" %-31s %s\n", "Load IA32_EFER:", + vmx_msr_bit_status(VM_EXIT_LOAD_HOST_EFER, all_0, all_1)); + printk(" %-31s %s\n", "Save VMX-preempt timer value:", + vmx_msr_bit_status(VM_EXIT_SAVE_PREEMPT_TIMER, all_0, all_1)); + printk(" %-31s %s\n", "Clear IA32_BNDCFGS:", + vmx_msr_bit_status(VM_EXIT_CLEAR_BNDCFGS, all_0, all_1)); + printk(" %-31s %s\n", "Conceal VM exits from Intel PT:", + vmx_msr_bit_status(0x01000000, all_0, all_1)); +} + +static void print_vmx_msr_entry_bits(u32 all_0, u32 all_1) +{ + printk(" %-31s %s\n", "Load debug controls:", + vmx_msr_bit_status(0x00000004, all_0, all_1)); + printk(" %-31s %s\n", "IA-32e mode guest:", + vmx_msr_bit_status(VM_ENTRY_IA32E_MODE, all_0, all_1)); + printk(" %-31s %s\n", "Entry to SMM:", + vmx_msr_bit_status(VM_ENTRY_SMM, all_0, all_1)); + printk(" %-31s %s\n", "Deactivate dual-mon treatment:", + vmx_msr_bit_status(VM_ENTRY_DEACT_DUAL_MONITOR, all_0, all_1)); + printk(" %-31s %s\n", "Load IA32_PERF_GLOBAL_CTRL:", + vmx_msr_bit_status(VM_ENTRY_LOAD_PERF_GLOBAL_CTRL, all_0, all_1)); + printk(" %-31s %s\n", "Load IA32_PAT:", + vmx_msr_bit_status(VM_ENTRY_LOAD_GUEST_PAT, all_0, all_1)); + printk(" %-31s %s\n", "Load IA32_EFER:", + vmx_msr_bit_status(VM_ENTRY_LOAD_GUEST_EFER, all_0, all_1)); + printk(" %-31s %s\n", "Load IA32_BNDCFGS:", + vmx_msr_bit_status(VM_ENTRY_LOAD_BNDCFGS, all_0, all_1)); + printk(" %-31s %s\n", "Conceal VM entries from PT:", + vmx_msr_bit_status(0x00020000, all_0, all_1)); +} + +static void print_vmx_misc_msr(struct vmx_msr_policy *p) +{ + printk("%-33s %#018lx\n", "MSR_IA32_VMX_MISC", p->misc.raw); + printk(" %-31s %d\n", "VMX-preemption timer scale:", + p->misc.preempt_timer_scale); + printk(" %-31s", "VM exit stores EFER LMA:"); + printk(" %s\n", btoa(p->misc.vmexit_stores_lma)); + printk(" %-31s", "HLT activity state:"); + printk(" %s\n", btoa(p->misc.hlt_activity_state)); + printk(" %-31s", "Shutdown activity state:"); + printk(" %s\n", btoa(p->misc.shutdown_activity_state)); + printk(" %-31s", "Wait-for-SIPI activity state:"); + printk(" %s\n", btoa(p->misc.wait_for_sipi_activity_state)); + printk(" %-31s", "Proc Trace in VMX entry:"); + printk(" %s\n", btoa(p->misc.pt_in_vmx)); + printk(" %-31s", "Read MSR_SMBASE in SMM:"); + printk(" %s\n", btoa(p->misc.ia32_smbase_support)); + printk(" %-31s", "CR3 targets:"); + printk(" %d\n", p->misc.cr3_target); + printk(" %-31s", "Max MSR-load/store list:"); + printk(" %d\n", p->misc.max_msr_load_count * 512); + printk(" %-31s", "VMXOFF must unblock SMIs:"); + printk(" %s\n", btoa(p->misc.ia32_smm_monitor_ctl_bit2)); + printk(" %-31s", "VMWRITE any MCS field:"); + printk(" %s\n", btoa(p->misc.vmwrite_all)); + printk(" %-31s", "VM entry SWI injection:"); + printk(" %s\n", btoa(p->misc.inject_ilen0_event)); + printk(" %-31s %#08x\n", "MSEG revision:", p->misc.mseg_revision_id); +} + +static void print_vmx_msr_procbased2_bits(u32 all_0, u32 all_1) +{ + printk(" %-31s %s\n", "Virtualize APIC accesses:", + vmx_msr_bit_status(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, + all_0, all_1)); + printk(" %-31s %s\n", "Enable EPT:", + vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_EPT, all_0, all_1)); + printk(" %-31s %s\n", "Descriptor-table exiting:", + vmx_msr_bit_status(SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING, + all_0, all_1)); + printk(" %-31s %s\n", "Enable RDTSCP:", + vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_RDTSCP, all_0, all_1)); + printk(" %-31s %s\n", "Virtualize x2APIC mode:", + vmx_msr_bit_status(SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE, + all_0, all_1)); + printk(" %-31s %s\n", "Enable VPID:", + vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_VPID, all_0, all_1)); + printk(" %-31s %s\n", "WBINVD exiting:", + vmx_msr_bit_status(SECONDARY_EXEC_WBINVD_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "Unrestricted guest:", + vmx_msr_bit_status(SECONDARY_EXEC_UNRESTRICTED_GUEST, all_0, all_1)); + printk(" %-31s %s\n", "APIC-register virtualization:", + vmx_msr_bit_status(SECONDARY_EXEC_APIC_REGISTER_VIRT, all_0, all_1)); + printk(" %-31s %s\n", "Virtual-interrupt delivery:", + vmx_msr_bit_status(SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY, + all_0, all_1)); + printk(" %-31s %s\n", "PAUSE-loop exiting:", + vmx_msr_bit_status(SECONDARY_EXEC_PAUSE_LOOP_EXITING, all_0, all_1)); + printk(" %-31s %s\n", "RDRAND exiting:", + vmx_msr_bit_status(0x00000800, all_0, all_1)); + printk(" %-31s %s\n", "Enable INVPCID:", + vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_INVPCID, all_0, all_1)); + printk(" %-31s %s\n", "Enable VM functions:", + vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_VM_FUNCTIONS, + all_0, all_1)); + printk(" %-31s %s\n", "VMCS shadowing:", + vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_VMCS_SHADOWING, + all_0, all_1)); + printk(" %-31s %s\n", "Enable ENCLS exiting:", + vmx_msr_bit_status(0x00008000, all_0, all_1)); + printk(" %-31s %s\n", "RDSEED exiting:", + vmx_msr_bit_status(0x00010000, all_0, all_1)); + printk(" %-31s %s\n", "Enable PML:", + vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_PML, all_0, all_1)); + printk(" %-31s %s\n", "EPT-violation #VE:", + vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS, + all_0, all_1)); + printk(" %-31s %s\n", "Conceal VMX non-root from PT:", + vmx_msr_bit_status(0x00080000, all_0, all_1)); + printk(" %-31s %s\n", "Enable XSAVES/XRSTORS:", + vmx_msr_bit_status(SECONDARY_EXEC_XSAVES, all_0, all_1)); + printk(" %-31s %s\n", "Mode-based exec ctrl for EPT:", + vmx_msr_bit_status(0x00400000, all_0, all_1)); + printk(" %-31s %s\n", "Use TSC scaling:", + vmx_msr_bit_status(SECONDARY_EXEC_TSC_SCALING, all_0, all_1)); +} + +static void print_vmx_ept_vpid_cap_msr(struct vmx_msr_policy *p) +{ + printk(" %-31s", "EPT exec-only:"); + printk("%s\n", btoa(p->ept_vpid_cap.exec_only_supported)); + printk(" %-31s", "Page-walk length 4:"); + printk("%s\n", btoa(p->ept_vpid_cap.walk_length_4_supported)); + printk(" %-31s", "EPT uncacheable:"); + printk("%s\n", btoa(p->ept_vpid_cap.memory_type_uc)); + printk(" %-31s", "EPT write-back:"); + printk("%s\n", btoa(p->ept_vpid_cap.memory_type_wb)); + printk(" %-31s", "EPT PDE 2MB superpages:"); + printk("%s\n", btoa(p->ept_vpid_cap.superpage_2mb)); + printk(" %-31s", "EPT PDE 1GB superpages:"); + printk("%s\n", btoa(p->ept_vpid_cap.superpage_1gb)); + printk(" %-31s", "INVEPT instruction:"); + printk("%s\n", btoa(p->ept_vpid_cap.invept_instruction)); + printk(" %-31s", "EPT accessed/dirty bits:"); + printk("%s\n", btoa(p->ept_vpid_cap.ad_bit)); + printk(" %-31s", "Advanced EPT violations:"); + printk("%s\n", btoa(p->ept_vpid_cap.advanced_ept_violations)); + printk(" %-31s", "INVEPT single-context:"); + printk("%s\n", btoa(p->ept_vpid_cap.invept_single_context)); + printk(" %-31s", "INVEPT all-context:"); + printk("%s\n", btoa(p->ept_vpid_cap.invept_all_context)); + printk(" %-31s", "INVVPID instruction:"); + printk("%s\n", btoa(p->ept_vpid_cap.invvpid_instruction)); + printk(" %-31s", "INVVPID individual-addr:"); + printk("%s\n", btoa(p->ept_vpid_cap.invvpid_individual_addr)); + printk(" %-31s", "INVVPID single-context:"); + printk("%s\n", btoa(p->ept_vpid_cap.invvpid_single_context)); + printk(" %-31s", "INVVPID all-context:"); + printk("%s\n", btoa(p->ept_vpid_cap.invvpid_all_context)); + printk(" %-31s", "INVVPID sgl-ctx-ret-gbls:"); + printk("%s\n", + btoa(p->ept_vpid_cap.invvpid_single_context_retaining_global)); +} + +static void print_vmx_msr_policy(struct vmx_msr_policy *policy) +{ + print_vmx_basic_msr(policy); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_PINBASED_CTLS", + policy->pinbased_ctls.raw); + print_vmx_msr_pinbased_bits(policy->pinbased_ctls.allowed_0.raw, + policy->pinbased_ctls.allowed_1.raw); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_PROCBASED_CTLS", + policy->procbased_ctls.raw); + print_vmx_msr_procbased_bits(policy->procbased_ctls.allowed_0.raw, + policy->procbased_ctls.allowed_1.raw); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_EXIT_CTLS", policy->exit_ctls.raw); + print_vmx_msr_exit_bits(policy->exit_ctls.allowed_0.raw, + policy->exit_ctls.allowed_1.raw); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_ENTRY_CTLS", + policy->entry_ctls.raw); + print_vmx_msr_entry_bits(policy->entry_ctls.allowed_0.raw, + policy->entry_ctls.allowed_1.raw); + + print_vmx_misc_msr(policy); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_CR0_FIXED0", + policy->cr0_fixed_0.raw); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_CR0_FIXED1", + policy->cr0_fixed_1.raw); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_CR4_FIXED0", + policy->cr4_fixed_0.raw); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_CR4_FIXED1", + policy->cr4_fixed_1.raw); + + printk("%-33s %#018lx\n", "MSR_IA32_VMX_VMCS_ENUM", + policy->vmcs_enum.raw); + printk(" %-31s %#x\n", "Max VMCS encoding index:", + policy->vmcs_enum.vmcs_encoding_max_idx); + + printk("%-33s ", "MSR_IA32_VMX_PROCBASED_CTLS2"); + if ( vmx_msr_available(policy, MSR_IA32_VMX_PROCBASED_CTLS2) ) + { + printk("%#018lx\n", policy->procbased_ctls2.raw); + print_vmx_msr_procbased2_bits(policy->procbased_ctls2.allowed_0.raw, + policy->procbased_ctls2.allowed_1.raw); + } + else + { + printk("N/A\n"); + } + + printk("%-33s ", "MSR_IA32_VMX_EPT_VPID_CAP"); + if ( vmx_msr_available(policy, MSR_IA32_VMX_EPT_VPID_CAP) ) + { + printk("%#018lx\n", policy->ept_vpid_cap.raw); + print_vmx_ept_vpid_cap_msr(policy); + } + else + { + printk("N/A\n"); + } + + printk("%-33s ", "MSR_IA32_VMX_TRUE_PINBASED_CTLS"); + if ( vmx_msr_available(policy, MSR_IA32_VMX_TRUE_PINBASED_CTLS) ) + { + printk("%#018lx\n", policy->true_pinbased_ctls.raw); + print_vmx_msr_pinbased_bits(policy->true_pinbased_ctls.allowed_0.raw, + policy->true_pinbased_ctls.allowed_1.raw); + } + else + { + printk("N/A\n"); + } + + printk("%-33s ", "MSR_IA32_VMX_TRUE_PROCBASED_CTLS"); + if ( vmx_msr_available(policy, MSR_IA32_VMX_TRUE_PROCBASED_CTLS) ) + { + printk("%#018lx\n", policy->true_procbased_ctls.raw); + print_vmx_msr_procbased_bits(policy->true_procbased_ctls.allowed_0.raw, + policy->true_procbased_ctls.allowed_1.raw); + } + else + { + printk("N/A\n"); + } + + printk("%-33s ", "MSR_IA32_VMX_TRUE_EXIT_CTLS"); + if ( vmx_msr_available(policy, MSR_IA32_VMX_TRUE_EXIT_CTLS) ) + { + printk("%#018lx\n", policy->true_exit_ctls.raw); + print_vmx_msr_exit_bits(policy->true_exit_ctls.allowed_0.raw, + policy->true_exit_ctls.allowed_1.raw); + } + else + { + printk("N/A\n"); + } + + printk("%-33s ", "MSR_IA32_VMX_TRUE_ENTRY_CTLS"); + if ( vmx_msr_available(policy, MSR_IA32_VMX_TRUE_ENTRY_CTLS) ) + { + printk("%#018lx\n", policy->true_entry_ctls.raw); + print_vmx_msr_entry_bits(policy->true_entry_ctls.allowed_0.raw, + policy->true_entry_ctls.allowed_1.raw); + } + else + { + printk("N/A\n"); + } + + printk("%-33s ", "MSR_IA32_VMX_VMFUNC"); + if ( vmx_msr_available(policy, MSR_IA32_VMX_VMFUNC) ) + { + printk("%#018lx\n", policy->vmfunc.raw); + printk(" %-31s %s\n", "EPTP switching:", + btoa(policy->vmfunc.eptp_switching)); + } + else + { + printk("N/A\n"); + } +} + int calculate_raw_policy(bool bsp) { struct vmx_msr_policy policy; @@ -219,6 +621,9 @@ int calculate_raw_policy(bool bsp) return -EINVAL; } + if ( bsp ) + print_vmx_msr_policy(&raw_vmx_msr_policy); + return 0; }