diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index da6ddf52f1..b142f29560 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -154,6 +154,408 @@ bool vmx_msr_available(struct vmx_msr_policy *p, uint32_t msr)
     return p->available & (1u << (msr - MSR_IA32_VMX_BASIC));
 }
 
+static char *vmx_msr_bit_status(u32 mask, u32 all_0, u32 all_1)
+{
+    if ( (all_0 & mask) && (all_1 & mask) )
+        return "1";
+    if ( !(all_0 & mask) && !(all_1 & mask) )
+        return "0";
+
+    return "0/1";
+}
+
+static char *btoa(uint32_t val)
+{
+    return val ? "yes" : "no";
+}
+
+static void print_vmx_basic_msr(struct vmx_msr_policy *p)
+{
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_BASIC",  p->basic.raw);
+    printk("  %-31s %#x\n", "VMCS revision:", p->basic.vmcs_revision_id);
+    printk("  %-31s %d\n", "VMCS/VMXON region size:",
+           p->basic.vmcs_region_size);
+    printk("  %-31s %s\n", "32-bit phys addr limit:",
+           btoa(p->basic.addresses_32bit));
+    printk("  %-31s %s\n", "Dual monitor mode:", btoa(p->basic.dual_monitor));
+    printk("  %-31s %d ", "VMCS memory type:", p->basic.memory_type);
+    switch ( p->basic.memory_type )
+    {
+        case MTRR_TYPE_UNCACHABLE:
+            printk("(Uncacheable)\n");
+            break;
+        case MTRR_TYPE_WRBACK:
+            printk("(Write Back)\n");
+            break;
+        default:
+            printk("(Unrecognized)\n");
+            break;
+    }
+    printk("  %-31s %s\n", "Report INS/OUTS VM exits:",
+           btoa(p->basic.ins_out_info));
+    printk("  %-31s %s\n", "Default1 CTLS clearable:",
+           btoa(p->basic.default1_zero));
+}
+
+static void print_vmx_msr_pinbased_bits(u32 all_0, u32 all_1)
+{
+    printk("  %-31s %s\n", "External-interrupt exiting:",
+           vmx_msr_bit_status(PIN_BASED_EXT_INTR_MASK, all_0, all_1));
+    printk("  %-31s %s\n", "NMI exiting:",
+           vmx_msr_bit_status(PIN_BASED_NMI_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "Virtual NMIs:",
+           vmx_msr_bit_status(PIN_BASED_VIRTUAL_NMIS, all_0, all_1));
+    printk("  %-31s %s\n", "VMX-preemption timer:",
+           vmx_msr_bit_status(PIN_BASED_PREEMPT_TIMER, all_0, all_1));
+    printk("  %-31s %s\n", "Posted interrupts:",
+           vmx_msr_bit_status(PIN_BASED_POSTED_INTERRUPT, all_0, all_1));
+}
+
+static void print_vmx_msr_procbased_bits(u32 all_0, u32 all_1)
+{
+    printk("  %-31s %s\n", "Interrupt-window exiting:",
+           vmx_msr_bit_status(CPU_BASED_VIRTUAL_INTR_PENDING, all_0, all_1));
+    printk("  %-31s %s\n", "Use TSC offsetting:",
+           vmx_msr_bit_status(CPU_BASED_USE_TSC_OFFSETING, all_0, all_1));
+    printk("  %-31s %s\n", "HLT exiting:",
+           vmx_msr_bit_status(CPU_BASED_HLT_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "INVLPG exiting:",
+           vmx_msr_bit_status(CPU_BASED_INVLPG_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "MWAIT exiting:",
+           vmx_msr_bit_status(CPU_BASED_MWAIT_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "RDPMC exiting:",
+           vmx_msr_bit_status(CPU_BASED_RDPMC_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "RDTSC exiting:",
+           vmx_msr_bit_status(CPU_BASED_RDTSC_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "CR3-load exiting:",
+           vmx_msr_bit_status(CPU_BASED_CR3_LOAD_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "CR3-store exiting:",
+           vmx_msr_bit_status(CPU_BASED_CR3_STORE_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "CR8-load exiting:",
+           vmx_msr_bit_status(CPU_BASED_CR8_LOAD_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "CR8-store exiting:",
+           vmx_msr_bit_status(CPU_BASED_CR8_STORE_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "Use TPR shadow:",
+           vmx_msr_bit_status(CPU_BASED_TPR_SHADOW, all_0, all_1));
+    printk("  %-31s %s\n", "NMI-window exiting:",
+           vmx_msr_bit_status(CPU_BASED_VIRTUAL_NMI_PENDING, all_0, all_1));
+    printk("  %-31s %s\n", "MOV-DR exiting:",
+           vmx_msr_bit_status(CPU_BASED_MOV_DR_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "Unconditional I/O exiting:",
+           vmx_msr_bit_status(CPU_BASED_UNCOND_IO_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "Use I/O bitmaps:",
+           vmx_msr_bit_status(CPU_BASED_ACTIVATE_IO_BITMAP, all_0, all_1));
+    printk("  %-31s %s\n", "Monitor trap flag:",
+           vmx_msr_bit_status(CPU_BASED_MONITOR_TRAP_FLAG, all_0, all_1));
+    printk("  %-31s %s\n", "Use MSR bitmaps:",
+           vmx_msr_bit_status(CPU_BASED_ACTIVATE_MSR_BITMAP, all_0, all_1));
+    printk("  %-31s %s\n", "MONITOR exiting:",
+           vmx_msr_bit_status(CPU_BASED_MONITOR_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "PAUSE exiting:",
+           vmx_msr_bit_status(CPU_BASED_PAUSE_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "Activate secondary controls:",
+           vmx_msr_bit_status(CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+                              all_0, all_1));
+}
+
+static void print_vmx_msr_exit_bits(u32 all_0, u32 all_1)
+{
+    printk("  %-31s %s\n", "Save debug controls:",
+           vmx_msr_bit_status(VM_EXIT_SAVE_DEBUG_CNTRLS, all_0, all_1));
+    printk("  %-31s %s\n", "Host address-space size:",
+           vmx_msr_bit_status(VM_EXIT_IA32E_MODE, all_0, all_1));
+    printk("  %-31s %s\n", "Load IA32_PERF_GLOBAL_CTRL:",
+           vmx_msr_bit_status(VM_EXIT_LOAD_PERF_GLOBAL_CTRL, all_0, all_1));
+    printk("  %-31s %s\n", "Acknowledge interrupt on exit:",
+           vmx_msr_bit_status(VM_EXIT_ACK_INTR_ON_EXIT, all_0, all_1));
+    printk("  %-31s %s\n", "Save IA32_PAT:",
+           vmx_msr_bit_status(VM_EXIT_SAVE_GUEST_PAT, all_0, all_1));
+    printk("  %-31s %s\n", "Load IA32_PAT:",
+           vmx_msr_bit_status(VM_EXIT_LOAD_HOST_PAT, all_0, all_1));
+    printk("  %-31s %s\n", "Save IA32_EFER:",
+           vmx_msr_bit_status(VM_EXIT_SAVE_GUEST_EFER, all_0, all_1));
+    printk("  %-31s %s\n", "Load IA32_EFER:",
+           vmx_msr_bit_status(VM_EXIT_LOAD_HOST_EFER, all_0, all_1));
+    printk("  %-31s %s\n", "Save VMX-preempt timer value:",
+           vmx_msr_bit_status(VM_EXIT_SAVE_PREEMPT_TIMER, all_0, all_1));
+    printk("  %-31s %s\n", "Clear IA32_BNDCFGS:",
+           vmx_msr_bit_status(VM_EXIT_CLEAR_BNDCFGS, all_0, all_1));
+    printk("  %-31s %s\n", "Conceal VM exits from Intel PT:",
+           vmx_msr_bit_status(0x01000000, all_0, all_1));
+}
+
+static void print_vmx_msr_entry_bits(u32 all_0, u32 all_1)
+{
+    printk("  %-31s %s\n", "Load debug controls:",
+           vmx_msr_bit_status(0x00000004, all_0, all_1));
+    printk("  %-31s %s\n", "IA-32e mode guest:",
+           vmx_msr_bit_status(VM_ENTRY_IA32E_MODE, all_0, all_1));
+    printk("  %-31s %s\n", "Entry to SMM:",
+           vmx_msr_bit_status(VM_ENTRY_SMM, all_0, all_1));
+    printk("  %-31s %s\n", "Deactivate dual-mon treatment:",
+           vmx_msr_bit_status(VM_ENTRY_DEACT_DUAL_MONITOR, all_0, all_1));
+    printk("  %-31s %s\n", "Load IA32_PERF_GLOBAL_CTRL:",
+           vmx_msr_bit_status(VM_ENTRY_LOAD_PERF_GLOBAL_CTRL, all_0, all_1));
+    printk("  %-31s %s\n", "Load IA32_PAT:",
+           vmx_msr_bit_status(VM_ENTRY_LOAD_GUEST_PAT, all_0, all_1));
+    printk("  %-31s %s\n", "Load IA32_EFER:",
+           vmx_msr_bit_status(VM_ENTRY_LOAD_GUEST_EFER, all_0, all_1));
+    printk("  %-31s %s\n", "Load IA32_BNDCFGS:",
+           vmx_msr_bit_status(VM_ENTRY_LOAD_BNDCFGS, all_0, all_1));
+    printk("  %-31s %s\n", "Conceal VM entries from PT:",
+           vmx_msr_bit_status(0x00020000, all_0, all_1));
+}
+
+static void print_vmx_misc_msr(struct vmx_msr_policy *p)
+{
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_MISC", p->misc.raw);
+    printk("  %-31s %d\n", "VMX-preemption timer scale:",
+           p->misc.preempt_timer_scale);
+    printk("  %-31s", "VM exit stores EFER LMA:");
+    printk(" %s\n", btoa(p->misc.vmexit_stores_lma));
+    printk("  %-31s", "HLT activity state:");
+    printk(" %s\n", btoa(p->misc.hlt_activity_state));
+    printk("  %-31s", "Shutdown activity state:");
+    printk(" %s\n", btoa(p->misc.shutdown_activity_state));
+    printk("  %-31s", "Wait-for-SIPI activity state:");
+    printk(" %s\n", btoa(p->misc.wait_for_sipi_activity_state));
+    printk("  %-31s", "Proc Trace in VMX entry:");
+    printk(" %s\n", btoa(p->misc.pt_in_vmx));
+    printk("  %-31s", "Read MSR_SMBASE in SMM:");
+    printk(" %s\n", btoa(p->misc.ia32_smbase_support));
+    printk("  %-31s", "CR3 targets:");
+    printk(" %d\n", p->misc.cr3_target);
+    printk("  %-31s", "Max MSR-load/store list:");
+    printk(" %d\n", p->misc.max_msr_load_count * 512);
+    printk("  %-31s", "VMXOFF must unblock SMIs:");
+    printk(" %s\n", btoa(p->misc.ia32_smm_monitor_ctl_bit2));
+    printk("  %-31s", "VMWRITE any MCS field:");
+    printk(" %s\n", btoa(p->misc.vmwrite_all));
+    printk("  %-31s", "VM entry SWI injection:");
+    printk(" %s\n", btoa(p->misc.inject_ilen0_event));
+    printk("  %-31s %#08x\n", "MSEG revision:", p->misc.mseg_revision_id);
+}
+
+static void print_vmx_msr_procbased2_bits(u32 all_0, u32 all_1)
+{
+    printk("  %-31s %s\n", "Virtualize APIC accesses:",
+           vmx_msr_bit_status(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
+                              all_0, all_1));
+    printk("  %-31s %s\n", "Enable EPT:",
+           vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_EPT, all_0, all_1));
+    printk("  %-31s %s\n", "Descriptor-table exiting:",
+           vmx_msr_bit_status(SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING,
+                              all_0, all_1));
+    printk("  %-31s %s\n", "Enable RDTSCP:",
+           vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_RDTSCP, all_0, all_1));
+    printk("  %-31s %s\n", "Virtualize x2APIC mode:",
+           vmx_msr_bit_status(SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE,
+                              all_0, all_1));
+    printk("  %-31s %s\n", "Enable VPID:",
+           vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_VPID, all_0, all_1));
+    printk("  %-31s %s\n", "WBINVD exiting:",
+           vmx_msr_bit_status(SECONDARY_EXEC_WBINVD_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "Unrestricted guest:",
+           vmx_msr_bit_status(SECONDARY_EXEC_UNRESTRICTED_GUEST, all_0, all_1));
+    printk("  %-31s %s\n", "APIC-register virtualization:",
+           vmx_msr_bit_status(SECONDARY_EXEC_APIC_REGISTER_VIRT, all_0, all_1));
+    printk("  %-31s %s\n", "Virtual-interrupt delivery:",
+           vmx_msr_bit_status(SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY,
+                              all_0, all_1));
+    printk("  %-31s %s\n", "PAUSE-loop exiting:",
+           vmx_msr_bit_status(SECONDARY_EXEC_PAUSE_LOOP_EXITING, all_0, all_1));
+    printk("  %-31s %s\n", "RDRAND exiting:",
+           vmx_msr_bit_status(0x00000800, all_0, all_1));
+    printk("  %-31s %s\n", "Enable INVPCID:",
+           vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_INVPCID, all_0, all_1));
+    printk("  %-31s %s\n", "Enable VM functions:",
+           vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_VM_FUNCTIONS,
+                              all_0, all_1));
+    printk("  %-31s %s\n", "VMCS shadowing:",
+           vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_VMCS_SHADOWING,
+                              all_0, all_1));
+    printk("  %-31s %s\n", "Enable ENCLS exiting:",
+           vmx_msr_bit_status(0x00008000, all_0, all_1));
+    printk("  %-31s %s\n", "RDSEED exiting:",
+           vmx_msr_bit_status(0x00010000, all_0, all_1));
+    printk("  %-31s %s\n", "Enable PML:",
+           vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_PML, all_0, all_1));
+    printk("  %-31s %s\n", "EPT-violation #VE:",
+           vmx_msr_bit_status(SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS,
+                              all_0, all_1));
+    printk("  %-31s %s\n", "Conceal VMX non-root from PT:",
+           vmx_msr_bit_status(0x00080000, all_0, all_1));
+    printk("  %-31s %s\n", "Enable XSAVES/XRSTORS:",
+           vmx_msr_bit_status(SECONDARY_EXEC_XSAVES, all_0, all_1));
+    printk("  %-31s %s\n", "Mode-based exec ctrl for EPT:",
+           vmx_msr_bit_status(0x00400000, all_0, all_1));
+    printk("  %-31s %s\n", "Use TSC scaling:",
+           vmx_msr_bit_status(SECONDARY_EXEC_TSC_SCALING, all_0, all_1));
+}
+
+static void print_vmx_ept_vpid_cap_msr(struct vmx_msr_policy *p)
+{
+        printk("   %-31s", "EPT exec-only:");
+        printk("%s\n", btoa(p->ept_vpid_cap.exec_only_supported));
+        printk("   %-31s", "Page-walk length 4:");
+        printk("%s\n", btoa(p->ept_vpid_cap.walk_length_4_supported));
+        printk("   %-31s", "EPT uncacheable:");
+        printk("%s\n", btoa(p->ept_vpid_cap.memory_type_uc));
+        printk("   %-31s", "EPT write-back:");
+        printk("%s\n", btoa(p->ept_vpid_cap.memory_type_wb));
+        printk("   %-31s", "EPT PDE 2MB superpages:");
+        printk("%s\n", btoa(p->ept_vpid_cap.superpage_2mb));
+        printk("   %-31s", "EPT PDE 1GB superpages:");
+        printk("%s\n", btoa(p->ept_vpid_cap.superpage_1gb));
+        printk("   %-31s", "INVEPT instruction:");
+        printk("%s\n", btoa(p->ept_vpid_cap.invept_instruction));
+        printk("   %-31s", "EPT accessed/dirty bits:");
+        printk("%s\n", btoa(p->ept_vpid_cap.ad_bit));
+        printk("   %-31s", "Advanced EPT violations:");
+        printk("%s\n", btoa(p->ept_vpid_cap.advanced_ept_violations));
+        printk("   %-31s", "INVEPT single-context:");
+        printk("%s\n", btoa(p->ept_vpid_cap.invept_single_context));
+        printk("   %-31s", "INVEPT all-context:");
+        printk("%s\n", btoa(p->ept_vpid_cap.invept_all_context));
+        printk("   %-31s", "INVVPID instruction:");
+        printk("%s\n", btoa(p->ept_vpid_cap.invvpid_instruction));
+        printk("   %-31s", "INVVPID individual-addr:");
+        printk("%s\n", btoa(p->ept_vpid_cap.invvpid_individual_addr));
+        printk("   %-31s", "INVVPID single-context:");
+        printk("%s\n", btoa(p->ept_vpid_cap.invvpid_single_context));
+        printk("   %-31s", "INVVPID all-context:");
+        printk("%s\n", btoa(p->ept_vpid_cap.invvpid_all_context));
+        printk("   %-31s", "INVVPID sgl-ctx-ret-gbls:");
+        printk("%s\n",
+               btoa(p->ept_vpid_cap.invvpid_single_context_retaining_global));
+}
+
+static void print_vmx_msr_policy(struct vmx_msr_policy *policy)
+{
+    print_vmx_basic_msr(policy);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_PINBASED_CTLS",
+                              policy->pinbased_ctls.raw);
+    print_vmx_msr_pinbased_bits(policy->pinbased_ctls.allowed_0.raw,
+                                policy->pinbased_ctls.allowed_1.raw);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_PROCBASED_CTLS",
+                              policy->procbased_ctls.raw);
+    print_vmx_msr_procbased_bits(policy->procbased_ctls.allowed_0.raw,
+                                 policy->procbased_ctls.allowed_1.raw);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_EXIT_CTLS", policy->exit_ctls.raw);
+    print_vmx_msr_exit_bits(policy->exit_ctls.allowed_0.raw,
+                            policy->exit_ctls.allowed_1.raw);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_ENTRY_CTLS",
+                              policy->entry_ctls.raw);
+    print_vmx_msr_entry_bits(policy->entry_ctls.allowed_0.raw,
+                             policy->entry_ctls.allowed_1.raw);
+
+    print_vmx_misc_msr(policy);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_CR0_FIXED0",
+                              policy->cr0_fixed_0.raw);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_CR0_FIXED1",
+                              policy->cr0_fixed_1.raw);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_CR4_FIXED0",
+                              policy->cr4_fixed_0.raw);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_CR4_FIXED1",
+                              policy->cr4_fixed_1.raw);
+
+    printk("%-33s %#018lx\n", "MSR_IA32_VMX_VMCS_ENUM",
+                              policy->vmcs_enum.raw);
+    printk("  %-31s %#x\n", "Max VMCS encoding index:",
+                            policy->vmcs_enum.vmcs_encoding_max_idx);
+
+    printk("%-33s ", "MSR_IA32_VMX_PROCBASED_CTLS2");
+    if ( vmx_msr_available(policy, MSR_IA32_VMX_PROCBASED_CTLS2) )
+    {
+        printk("%#018lx\n", policy->procbased_ctls2.raw);
+        print_vmx_msr_procbased2_bits(policy->procbased_ctls2.allowed_0.raw,
+                                      policy->procbased_ctls2.allowed_1.raw);
+    }
+    else
+    {
+        printk("N/A\n");
+    }
+
+    printk("%-33s ", "MSR_IA32_VMX_EPT_VPID_CAP");
+    if ( vmx_msr_available(policy, MSR_IA32_VMX_EPT_VPID_CAP) )
+    {
+        printk("%#018lx\n", policy->ept_vpid_cap.raw);
+        print_vmx_ept_vpid_cap_msr(policy);
+    }
+    else
+    {
+        printk("N/A\n");
+    }
+
+    printk("%-33s ", "MSR_IA32_VMX_TRUE_PINBASED_CTLS");
+    if ( vmx_msr_available(policy, MSR_IA32_VMX_TRUE_PINBASED_CTLS) )
+    {
+        printk("%#018lx\n", policy->true_pinbased_ctls.raw);
+        print_vmx_msr_pinbased_bits(policy->true_pinbased_ctls.allowed_0.raw,
+                                    policy->true_pinbased_ctls.allowed_1.raw);
+    }
+    else
+    {
+        printk("N/A\n");
+    }
+
+    printk("%-33s ", "MSR_IA32_VMX_TRUE_PROCBASED_CTLS");
+    if ( vmx_msr_available(policy, MSR_IA32_VMX_TRUE_PROCBASED_CTLS) )
+    {
+        printk("%#018lx\n", policy->true_procbased_ctls.raw);
+        print_vmx_msr_procbased_bits(policy->true_procbased_ctls.allowed_0.raw,
+                                     policy->true_procbased_ctls.allowed_1.raw);
+    }
+    else
+    {
+        printk("N/A\n");
+    }
+
+    printk("%-33s ", "MSR_IA32_VMX_TRUE_EXIT_CTLS");
+    if ( vmx_msr_available(policy, MSR_IA32_VMX_TRUE_EXIT_CTLS) )
+    {
+        printk("%#018lx\n", policy->true_exit_ctls.raw);
+        print_vmx_msr_exit_bits(policy->true_exit_ctls.allowed_0.raw,
+                                policy->true_exit_ctls.allowed_1.raw);
+    }
+    else
+    {
+        printk("N/A\n");
+    }
+
+    printk("%-33s ", "MSR_IA32_VMX_TRUE_ENTRY_CTLS");
+    if ( vmx_msr_available(policy, MSR_IA32_VMX_TRUE_ENTRY_CTLS) )
+    {
+        printk("%#018lx\n", policy->true_entry_ctls.raw);
+        print_vmx_msr_entry_bits(policy->true_entry_ctls.allowed_0.raw,
+                                 policy->true_entry_ctls.allowed_1.raw);
+    }
+    else
+    {
+        printk("N/A\n");
+    }
+
+    printk("%-33s ", "MSR_IA32_VMX_VMFUNC");
+    if ( vmx_msr_available(policy, MSR_IA32_VMX_VMFUNC) )
+    {
+        printk("%#018lx\n", policy->vmfunc.raw);
+        printk("  %-31s %s\n", "EPTP switching:",
+                             btoa(policy->vmfunc.eptp_switching));
+    }
+    else
+    {
+        printk("N/A\n");
+    }
+}
+
 int calculate_raw_policy(bool bsp)
 {
     struct vmx_msr_policy policy;
@@ -219,6 +621,9 @@ int calculate_raw_policy(bool bsp)
         return -EINVAL;
     }
 
+    if ( bsp )
+        print_vmx_msr_policy(&raw_vmx_msr_policy);
+
     return 0;
 }
 
