From patchwork Fri Jul 7 03:53:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9829527 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CF11C602CA for ; Fri, 7 Jul 2017 03:56:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B736228504 for ; Fri, 7 Jul 2017 03:56:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ABE60285A4; Fri, 7 Jul 2017 03:56:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E37FC2858F for ; Fri, 7 Jul 2017 03:56:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dTKKu-0002BN-PY; Fri, 07 Jul 2017 03:53:44 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dTKKt-0002B6-QH for xen-devel@lists.xen.org; Fri, 07 Jul 2017 03:53:43 +0000 Received: from [85.158.137.68] by server-2.bemta-3.messagelabs.com id 1C/D0-22472-7C50F595; Fri, 07 Jul 2017 03:53:43 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRWlGSWpSXmKPExsVywNykQvcYa3y kwa4lEhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8a+zpWsBXdVKnrWLmNuYHwp3cXIxSEkMJ1R Yn7vBOYuRk4OCQFeiSPLZrBC2P4SOzd/Y4Yo6mWUmPBpLTtIgk1AX2LF44NgRSIC0hLXPl9mB LGZBaolJk6fA2YLC9hJvHh5CsxmEVCV2NF/A6yXV8BW4sWBVSwQC+QldrVdBJvDCVTffnEr2B FCQDUPVq1lmcDIu4CRYRWjenFqUVlqka6RXlJRZnpGSW5iZo6uoYGxXm5qcXFiempOYlKxXnJ +7iZGYDjUMzAw7mA81ex8iFGSg0lJlPfMzbhIIb6k/JTKjMTijPii0pzU4kOMMhwcShK8a1ni I4UEi1LTUyvSMnOAgQmTluDgURLh3QfSyltckJhbnJkOkTrFqMvxasL/b0xCLHn5ealS4ryrQ GYIgBRllObBjYBFySVGWSlhXkYGBgYhnoLUotzMElT5V4ziHIxKwrzbQKbwZOaVwG16BXQEE9 ARio0xIEeUJCKkpBoYM3NU3hbK6Caecnu5SYex5Of0yEx94SCxO5uerDAzPOOx43fNN5lNSue M9sZESjnP3+8T7re+VvO648cFMmniT1dNb/bnMV3Yr7Lf7dfmnMkb6yUb/yWkLbNJj3s7ude7 7+O8ssrpHxN8b65fMueol9RNtejbKYcZBe4+uj+5r/HTpyy+s7auSizFGYmGWsxFxYkAJ+0nH I0CAAA= X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-14.tower-31.messagelabs.com!1499399618!104177186!2 X-Originating-IP: [192.55.52.120] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.25; banners=-,-,- X-VirusChecked: Checked Received: (qmail 54971 invoked from network); 7 Jul 2017 03:53:42 -0000 Received: from mga04.intel.com (HELO mga04.intel.com) (192.55.52.120) by server-14.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 7 Jul 2017 03:53:42 -0000 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jul 2017 20:53:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,320,1496127600"; d="scan'208";a="123632510" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.142]) by fmsmga005.fm.intel.com with ESMTP; 06 Jul 2017 20:53:40 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Fri, 7 Jul 2017 11:53:09 +0800 Message-Id: <20170707035314.15659-3-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170707035314.15659-1-haozhong.zhang@intel.com> References: <20170707035314.15659-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH v7 2/7] x86/vmce: emulate MSR_IA32_MCG_EXT_CTL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then allow guest to read/write MSR_IA32_MCG_EXT_CTL. Signed-off-by: Haozhong Zhang --- Cc: Jan Beulich Cc: Andrew Cooper --- xen/arch/x86/cpu/mcheck/vmce.c | 34 +++++++++++++++++++++++++++++++++- xen/arch/x86/domctl.c | 2 ++ xen/include/asm-x86/mce.h | 1 + xen/include/public/arch-x86/hvm/save.h | 1 + 4 files changed, 37 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 1356f611ab..060e2d0582 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -91,6 +91,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt) v->arch.vmce.mcg_cap = ctxt->caps; v->arch.vmce.bank[0].mci_ctl2 = ctxt->mci_ctl2_bank0; v->arch.vmce.bank[1].mci_ctl2 = ctxt->mci_ctl2_bank1; + v->arch.vmce.mcg_ext_ctl = ctxt->mcg_ext_ctl; return 0; } @@ -200,6 +201,26 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val) mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_CTL %#"PRIx64"\n", cur, *val); break; + case MSR_IA32_MCG_EXT_CTL: + /* + * If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, the LMCE and LOCK + * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen, so it + * does not need to check them here. + */ + if ( cur->arch.vmce.mcg_cap & MCG_LMCE_P ) + { + *val = cur->arch.vmce.mcg_ext_ctl; + mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n", + cur, *val); + } + else + { + ret = -1; + mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL, not supported\n", + cur); + } + break; + default: ret = mce_bank_msr(cur, msr) ? bank_mce_rdmsr(cur, msr, val) : 0; break; @@ -309,6 +330,16 @@ int vmce_wrmsr(uint32_t msr, uint64_t val) mce_printk(MCE_VERBOSE, "MCE: %pv: MCG_CAP is r/o\n", cur); break; + case MSR_IA32_MCG_EXT_CTL: + if ( (cur->arch.vmce.mcg_cap & MCG_LMCE_P) && + !(val & ~MCG_EXT_CTL_LMCE_EN) ) + cur->arch.vmce.mcg_ext_ctl = val; + else + ret = -1; + mce_printk(MCE_VERBOSE, "MCE: %pv: wr MCG_EXT_CTL %"PRIx64"%s\n", + cur, val, (ret == -1) ? ", not supported" : ""); + break; + default: ret = mce_bank_msr(cur, msr) ? bank_mce_wrmsr(cur, msr, val) : 0; break; @@ -327,7 +358,8 @@ static int vmce_save_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h) struct hvm_vmce_vcpu ctxt = { .caps = v->arch.vmce.mcg_cap, .mci_ctl2_bank0 = v->arch.vmce.bank[0].mci_ctl2, - .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2 + .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2, + .mcg_ext_ctl = v->arch.vmce.mcg_ext_ctl, }; err = hvm_save_entry(VMCE_VCPU, v->vcpu_id, h, &ctxt); diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 5cd2af76bb..0e901e7298 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -312,6 +312,7 @@ static int vcpu_set_vmce(struct vcpu *v, */ static const unsigned int valid_vmce_size[] = { sizeof(evc->vmce), + sizeof(evc->vmce) - sizeof(evc->vmce.mcg_ext_ctl), sizeof(evc->mcg_cap), 0, }; @@ -904,6 +905,7 @@ long arch_do_domctl( evc->vmce.caps = v->arch.vmce.mcg_cap; evc->vmce.mci_ctl2_bank0 = v->arch.vmce.bank[0].mci_ctl2; evc->vmce.mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2; + evc->vmce.mcg_ext_ctl = v->arch.vmce.mcg_ext_ctl; ret = 0; vcpu_unpause(v); diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h index 56ad1f92dd..35f9962638 100644 --- a/xen/include/asm-x86/mce.h +++ b/xen/include/asm-x86/mce.h @@ -27,6 +27,7 @@ struct vmce_bank { struct vmce { uint64_t mcg_cap; uint64_t mcg_status; + uint64_t mcg_ext_ctl; spinlock_t lock; struct vmce_bank bank[GUEST_MC_BANK_NUM]; }; diff --git a/xen/include/public/arch-x86/hvm/save.h b/xen/include/public/arch-x86/hvm/save.h index 816973b9c2..fd7bf3fb38 100644 --- a/xen/include/public/arch-x86/hvm/save.h +++ b/xen/include/public/arch-x86/hvm/save.h @@ -610,6 +610,7 @@ struct hvm_vmce_vcpu { uint64_t caps; uint64_t mci_ctl2_bank0; uint64_t mci_ctl2_bank1; + uint64_t mcg_ext_ctl; }; DECLARE_HVM_SAVE_TYPE(VMCE_VCPU, 18, struct hvm_vmce_vcpu);