From patchwork Wed Jul 12 02:04:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9835803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 88A0E602BD for ; Wed, 12 Jul 2017 02:07:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 571B9283BB for ; Wed, 12 Jul 2017 02:07:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4B6CD2845C; Wed, 12 Jul 2017 02:07:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8E643283BB for ; Wed, 12 Jul 2017 02:07:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dV71Q-0004Lz-Tp; Wed, 12 Jul 2017 02:05:00 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dV71P-0004LD-Hl for xen-devel@lists.xen.org; Wed, 12 Jul 2017 02:04:59 +0000 Received: from [85.158.143.35] by server-4.bemta-6.messagelabs.com id 5F/E8-02962-AC385695; Wed, 12 Jul 2017 02:04:58 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeJIrShJLcpLzFFi42Jpa+uQ0D3VnBp p8HAnt8WSj4tZHBg9ju7+zRTAGMWamZeUX5HAmvHvhFzB9oCKKYsbGRsYF9h1MXJxCAlMZ5RY 9O0LWxcjJ4eEAK/EkWUzWCFsf4m/C1+zQxT1MkosP7yDHSTBJqAvseLxQbAiEQFpiWufLzOCF DELHGWU+NS+HCjBwSEsEC9xYmMWSA2LgKrEj3+bGEFsXgFricdnLzBDLJCX2NV2EWwOp4CNxP /Tq8BsIaCaBdc7mCcw8i5gZFjFqFGcWlSWWqRrZKyXVJSZnlGSm5iZo2toYKaXm1pcnJiempO YVKyXnJ+7iREYDgxAsIPxz/zAQ4ySHExKorw78lMjhfiS8lMqMxKLM+KLSnNSiw8xynBwKEnw nmoCygkWpaanVqRl5gADEyYtwcGjJMLrHQ2U5i0uSMwtzkyHSJ1iNObYsHr9FyaOVxP+f2MSY snLz0uVEufdDzJJAKQ0ozQPbhAsYi4xykoJ8zICnSbEU5BalJtZgir/ilGcg1FJmDcAZApPZl 4J3L5XQKcwAZ2yJjsF5JSSRISUVAOjxt6wWAW3yUu2L5p66JDZlA8LxDfqZO41/hhu6vJKIOz Pxxx264W7f0Wdua112rar57Frqo1O8GzBA4tuyOYcZxGR3GoZwtuwofROkBbrOvH/rc+Fdfw1 TWZvjlVtYU6sfc747lB50kulrsC285L3p3bcX1otaNa/v1rbuSW9MPgs//xwtz1KLMUZiYZaz EXFiQCrg29JkwIAAA== X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-6.tower-21.messagelabs.com!1499825092!49747596!4 X-Originating-IP: [134.134.136.24] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjQgPT4gMzkwOTcx\n X-StarScan-Received: X-StarScan-Version: 9.4.25; banners=-,-,- X-VirusChecked: Checked Received: (qmail 15322 invoked from network); 12 Jul 2017 02:04:57 -0000 Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by server-6.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 12 Jul 2017 02:04:57 -0000 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jul 2017 19:04:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,347,1496127600"; d="scan'208";a="877806789" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.142]) by FMSMGA003.fm.intel.com with ESMTP; 11 Jul 2017 19:04:55 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Wed, 12 Jul 2017 10:04:37 +0800 Message-Id: <20170712020440.777-5-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170712020440.777-1-haozhong.zhang@intel.com> References: <20170712020440.777-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Ian Jackson , Wei Liu , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH v9 4/7] x86/vmce, tools/libxl: expose LMCE capability in guest MSR_IA32_MCG_CAP X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP If LMCE is supported by host and ' mca_caps = [ "lmce" ] ' is present in xl config, the LMCE capability will be exposed in guest MSR_IA32_MCG_CAP. By default, LMCE is not exposed to guest so as to keep the backwards migration compatibility. Signed-off-by: Haozhong Zhang Reviewed-by: Jan Beulich for hypervisor side Acked-by: Wei Liu --- Cc: Ian Jackson Cc: Wei Liu Cc: Jan Beulich Cc: Andrew Cooper --- docs/man/xl.cfg.pod.5.in | 24 ++++++++++++++++++++++++ tools/libxc/xc_sr_save_x86_hvm.c | 1 + tools/libxl/libxl.h | 7 +++++++ tools/libxl/libxl_dom.c | 15 +++++++++++++++ tools/libxl/libxl_types.idl | 1 + tools/xl/xl_parse.c | 31 +++++++++++++++++++++++++++++-- xen/arch/x86/cpu/mcheck/mce.h | 1 + xen/arch/x86/cpu/mcheck/mce_intel.c | 2 +- xen/arch/x86/cpu/mcheck/vmce.c | 19 ++++++++++++++++++- xen/arch/x86/hvm/hvm.c | 5 +++++ xen/include/asm-x86/mce.h | 1 + xen/include/public/hvm/params.h | 7 ++++++- 12 files changed, 109 insertions(+), 5 deletions(-) diff --git a/docs/man/xl.cfg.pod.5.in b/docs/man/xl.cfg.pod.5.in index ff3203550f..79cb2eaea7 100644 --- a/docs/man/xl.cfg.pod.5.in +++ b/docs/man/xl.cfg.pod.5.in @@ -2173,6 +2173,30 @@ natively or via hardware backwards compatibility support. =back +=head3 x86 + +=over 4 + +=item B + +(HVM only) Enable MCA capabilities besides default ones enabled +by Xen hypervisor for the HVM domain. "CAP" can be one in the +following list: + +=over 4 + +=item B<"lmce"> + +Intel local MCE + +=item B + +No MCA capabilities in above list are enabled. + +=back + +=back + =head1 SEE ALSO =over 4 diff --git a/tools/libxc/xc_sr_save_x86_hvm.c b/tools/libxc/xc_sr_save_x86_hvm.c index fc5c6ea93e..e17bb59146 100644 --- a/tools/libxc/xc_sr_save_x86_hvm.c +++ b/tools/libxc/xc_sr_save_x86_hvm.c @@ -77,6 +77,7 @@ static int write_hvm_params(struct xc_sr_context *ctx) HVM_PARAM_IOREQ_SERVER_PFN, HVM_PARAM_NR_IOREQ_SERVER_PAGES, HVM_PARAM_X87_FIP_WIDTH, + HVM_PARAM_MCA_CAP, }; xc_interface *xch = ctx->xch; diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h index cf8687aa7e..7cf0f31f68 100644 --- a/tools/libxl/libxl.h +++ b/tools/libxl/libxl.h @@ -922,6 +922,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, const libxl_mac *src); * If this is defined, the Code and Data Prioritization feature is supported. */ #define LIBXL_HAVE_PSR_CDP 1 + +/* + * LIBXL_HAVE_MCA_CAPS + * + * If this is defined, setting MCA capabilities for HVM domain is supported. + */ +#define LIBXL_HAVE_MCA_CAPS 1 #endif /* diff --git a/tools/libxl/libxl_dom.c b/tools/libxl/libxl_dom.c index 5d914a59ee..f54fd49a73 100644 --- a/tools/libxl/libxl_dom.c +++ b/tools/libxl/libxl_dom.c @@ -279,6 +279,17 @@ err: libxl_bitmap_dispose(&enlightenments); return ERROR_FAIL; } + +static int hvm_set_mca_capabilities(libxl__gc *gc, uint32_t domid, + libxl_domain_build_info *const info) +{ + unsigned long caps = info->u.hvm.mca_caps; + + if (!caps) + return 0; + + return xc_hvm_param_set(CTX->xch, domid, HVM_PARAM_MCA_CAP, caps); +} #endif static void hvm_set_conf_params(xc_interface *handle, uint32_t domid, @@ -440,6 +451,10 @@ int libxl__build_pre(libxl__gc *gc, uint32_t domid, rc = hvm_set_viridian_features(gc, domid, info); if (rc) return rc; + + rc = hvm_set_mca_capabilities(gc, domid, info); + if (rc) + return rc; #endif } diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl index 22044259f3..8a9849c643 100644 --- a/tools/libxl/libxl_types.idl +++ b/tools/libxl/libxl_types.idl @@ -564,6 +564,7 @@ libxl_domain_build_info = Struct("domain_build_info",[ ("serial_list", libxl_string_list), ("rdm", libxl_rdm_reserve), ("rdm_mem_boundary_memkb", MemKB), + ("mca_caps", uint64), ])), ("pv", Struct(None, [("kernel", string), ("slack_memkb", MemKB), diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c index 856a304b30..5c2bf17222 100644 --- a/tools/xl/xl_parse.c +++ b/tools/xl/xl_parse.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -813,8 +814,9 @@ void parse_config_data(const char *config_source, XLU_Config *config; XLU_ConfigList *cpus, *vbds, *nics, *pcis, *cvfbs, *cpuids, *vtpms, *usbctrls, *usbdevs, *p9devs; - XLU_ConfigList *channels, *ioports, *irqs, *iomem, *viridian, *dtdevs; - int num_ioports, num_irqs, num_iomem, num_cpus, num_viridian; + XLU_ConfigList *channels, *ioports, *irqs, *iomem, *viridian, *dtdevs, + *mca_caps; + int num_ioports, num_irqs, num_iomem, num_cpus, num_viridian, num_mca_caps; int pci_power_mgmt = 0; int pci_msitranslate = 0; int pci_permissive = 0; @@ -1182,6 +1184,31 @@ void parse_config_data(const char *config_source, if (!xlu_cfg_get_long (config, "rdm_mem_boundary", &l, 0)) b_info->u.hvm.rdm_mem_boundary_memkb = l * 1024; + + switch (xlu_cfg_get_list(config, "mca_caps", + &mca_caps, &num_mca_caps, 1)) + { + case 0: /* Success */ + for (i = 0; i < num_mca_caps; i++) { + buf = xlu_cfg_get_listitem(mca_caps, i); + if (!strcmp(buf, "lmce")) + b_info->u.hvm.mca_caps |= XEN_HVM_MCA_CAP_LMCE; + else { + fprintf(stderr, "ERROR: unrecognized MCA capability '%s'.\n", + buf); + exit(-ERROR_FAIL); + } + } + break; + + case ESRCH: /* Option not present */ + break; + + default: + fprintf(stderr, "ERROR: unable to parse mca_caps.\n"); + exit(-ERROR_FAIL); + } + break; case LIBXL_DOMAIN_TYPE_PV: { diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 4f13791948..664161a2af 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -38,6 +38,7 @@ enum mcheck_type { }; extern uint8_t cmci_apic_vector; +extern bool lmce_support; /* Init functions */ enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *c); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 5cb49ca697..4c001b407f 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -30,7 +30,7 @@ boolean_param("mce_fb", mce_force_broadcast); static int __read_mostly nr_intel_ext_msrs; /* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */ -static bool __read_mostly lmce_support; +bool __read_mostly lmce_support; /* Intel SDM define bit15~bit0 of IA32_MCi_STATUS as the MC error code */ #define INTEL_MCCOD_MASK 0xFFFF diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index e2b3c5b8cc..62faae49c6 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -75,7 +75,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt) unsigned long guest_mcg_cap; if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) - guest_mcg_cap = INTEL_GUEST_MCG_CAP; + guest_mcg_cap = INTEL_GUEST_MCG_CAP | MCG_LMCE_P; else guest_mcg_cap = AMD_GUEST_MCG_CAP; @@ -547,3 +547,20 @@ int unmmap_broken_page(struct domain *d, mfn_t mfn, unsigned long gfn) return rc; } +int vmce_enable_mca_cap(struct domain *d, uint64_t cap) +{ + struct vcpu *v; + + if ( cap & ~XEN_HVM_MCA_CAP_MASK ) + return -EINVAL; + + if ( cap & XEN_HVM_MCA_CAP_LMCE ) + { + if ( !lmce_support ) + return -EINVAL; + for_each_vcpu(d, v) + v->arch.vmce.mcg_cap |= MCG_LMCE_P; + } + + return 0; +} diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 3ed6ec468d..8145385747 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4035,6 +4035,7 @@ static int hvm_allow_set_param(struct domain *d, case HVM_PARAM_IOREQ_SERVER_PFN: case HVM_PARAM_NR_IOREQ_SERVER_PAGES: case HVM_PARAM_ALTP2M: + case HVM_PARAM_MCA_CAP: if ( value != 0 && a->value != value ) rc = -EEXIST; break; @@ -4246,6 +4247,10 @@ static int hvmop_set_param( (0x10000 / 8) + 1) << 32); a.value |= VM86_TSS_UPDATED; break; + + case HVM_PARAM_MCA_CAP: + rc = vmce_enable_mca_cap(d, a.value); + break; } if ( rc != 0 ) diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h index 35f9962638..d2933c91bf 100644 --- a/xen/include/asm-x86/mce.h +++ b/xen/include/asm-x86/mce.h @@ -38,6 +38,7 @@ extern int vmce_restore_vcpu(struct vcpu *, const struct hvm_vmce_vcpu *); extern int vmce_wrmsr(uint32_t msr, uint64_t val); extern int vmce_rdmsr(uint32_t msr, uint64_t *val); extern bool vmce_has_lmce(const struct vcpu *v); +extern int vmce_enable_mca_cap(struct domain *d, uint64_t cap); extern unsigned int nr_mce_banks; diff --git a/xen/include/public/hvm/params.h b/xen/include/public/hvm/params.h index 1f3ed0906d..2ec2e7c80f 100644 --- a/xen/include/public/hvm/params.h +++ b/xen/include/public/hvm/params.h @@ -274,6 +274,11 @@ */ #define HVM_PARAM_VM86_TSS_SIZED 37 -#define HVM_NR_PARAMS 38 +/* Enable MCA capabilities. */ +#define HVM_PARAM_MCA_CAP 38 +#define XEN_HVM_MCA_CAP_LMCE (xen_mk_ullong(1) << 0) +#define XEN_HVM_MCA_CAP_MASK XEN_HVM_MCA_CAP_LMCE + +#define HVM_NR_PARAMS 39 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */