From patchwork Tue Sep 12 10:03:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 9948887 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CBCD8603F3 for ; Tue, 12 Sep 2017 10:06:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BBA4D28EC3 for ; Tue, 12 Sep 2017 10:06:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B07E428EC7; Tue, 12 Sep 2017 10:06:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7F4E628ED1 for ; Tue, 12 Sep 2017 10:06:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dri37-0003Qt-Cn; Tue, 12 Sep 2017 10:04:09 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dri36-0003Ly-0q for xen-devel@lists.xen.org; Tue, 12 Sep 2017 10:04:08 +0000 Received: from [85.158.137.68] by server-7.bemta-3.messagelabs.com id 89/DE-02224-711B7B95; Tue, 12 Sep 2017 10:04:07 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTVds4/Z Ig1vT9C2WfFzM4sDocXT3b6YAxijWzLyk/IoE1oyF264zFzwSrOh/cIyxgfEXXxcjF4eQwGZG ibPfG1khnNOMEhM2bWbpYuTkYBPQlLjz+RMTiC0iIC1x7fNlRhCbWSBS4vCHH+xdjBwcwgIuE mc/iYGYLAKqEmfOxoNU8ApYSkw5dBpsioSAvMSutousIDYnUHzFx19sILaQgIXE95c/GCcwci 9gZFjFqFGcWlSWWqRrZK6XVJSZnlGSm5iZo2toYKyXm1pcnJiempOYVKyXnJ+7iRHo3XoGBsY djC17/Q4xSnIwKYnyHlm/PVKILyk/pTIjsTgjvqg0J7X4EKMMB4eSBC/7BqCcYFFqempFWmYO MMxg0hIcPEoivAEgad7igsTc4sx0iNQpRl2Ojpt3/zAJseTl56VKifO+AZkvAFKUUZoHNwIW8 pcYZaWEeRkZGBiEeApSi3IzS1DlXzGKczAqCfPKgaziycwrgdv0CugIJqAjeC5tATmiJBEhJd XAaO3QySPOv/HEAumjYm/uH9dgUHIUWttc4bpGrbuDWf3JKttDBbaL7AVk4rIOzC5SPOynGZZ uIlOcd0FgWaRea/f1XwEiXlcc9QXl9Wdv4T85VfvvsUU6c6a0agfmWZ3Xt14yU87t4BPXiXUr P/hmfztU4nhz94o1aaeXpO3I/qnZ+kXm0/4FSizFGYmGWsxFxYkAvPUQ2nQCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-10.tower-31.messagelabs.com!1505210646!113666026!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG, UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3041 invoked from network); 12 Sep 2017 10:04:06 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-10.tower-31.messagelabs.com with SMTP; 12 Sep 2017 10:04:06 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 04E7C165D; Tue, 12 Sep 2017 03:04:06 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 16C7C3F578; Tue, 12 Sep 2017 03:04:04 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 12 Sep 2017 11:03:28 +0100 Message-Id: <20170912100330.2168-23-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170912100330.2168-1-julien.grall@arm.com> References: <20170912100330.2168-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v2 22/24] xen/arm: mm: Embed permission in the flags X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently, it is not possible to specify the permission of a new mapping. It would be necessary to use the function modify_xen_mappings with a different set of flags. Introduce a couple of new flags for the permissions (Non-eXecutable, Read-Only) and also provides definition that combine the memory attribute and permission for common combinations. PAGE_HYPERVISOR is now an alias to PAGE_HYPERVISOR_RW (read-write, non-executable mappings). This does not affect the current mapping using PAGE_HYPERVISOR because Xen is currently forcing all the mapping to be non-executable by default (see mfn_to_xen_entry). A follow-up patch will change modify_xen_mappings to use the new flags. Signed-off-by: Julien Grall --- Changes in v2: - Update the commit message --- xen/include/asm-arm/page.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 4022b7dc33..814ed126ec 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -66,12 +66,28 @@ * Layout of the flags used for updating the hypervisor page tables * * [0:2] Memory Attribute Index + * [3:4] Permission flags */ #define PAGE_AI_MASK(x) ((x) & 0x7U) -#define PAGE_HYPERVISOR (MT_NORMAL) -#define PAGE_HYPERVISOR_NOCACHE (MT_DEVICE_nGnRE) -#define PAGE_HYPERVISOR_WC (MT_NORMAL_NC) +#define _PAGE_XN_BIT 3 +#define _PAGE_RO_BIT 4 +#define _PAGE_XN (1U << _PAGE_XN_BIT) +#define _PAGE_RO (1U << _PAGE_RO_BIT) +#define PAGE_XN_MASK(x) (((x) >> _PAGE_XN_BIT) & 0x1U) +#define PAGE_RO_MASK(x) (((x) >> _PAGE_RO_BIT) & 0x1U) + +/* Device memory will always be mapped read-write non-executable. */ +#define _PAGE_DEVICE _PAGE_XN +#define _PAGE_NORMAL MT_NORMAL + +#define PAGE_HYPERVISOR_RO (_PAGE_NORMAL|_PAGE_RO|_PAGE_XN) +#define PAGE_HYPERVISOR_RX (_PAGE_NORMAL|_PAGE_RO) +#define PAGE_HYPERVISOR_RW (_PAGE_NORMAL|_PAGE_XN) + +#define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW +#define PAGE_HYPERVISOR_NOCACHE (_PAGE_DEVICE|MT_DEVICE_nGnRE) +#define PAGE_HYPERVISOR_WC (_PAGE_DEVICE|MT_NORMAL_NC) /* * Defines for changing the hypervisor PTE .ro and .nx bits. This is only to be