diff mbox

[v2,08/24] xen/arm: Add FnV field in hsr_*abt

Message ID 20170912100330.2168-9-julien.grall@arm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Julien Grall Sept. 12, 2017, 10:03 a.m. UTC 
FnV (FAR not Valid) bit was introduced by ARMv8 in both AArch32 and
AArch64 (See D7-2275, D7-2277, G6-4958, G6-4962 in ARM DDI 0487B.a).

Note the new revision of ARMv8 defined more bits in HSR. They haven't
been added at the moment because we have no use of them in Xen.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---

    Changes in v2:
        - Expand the commit message to explain why the other bits have
        not been added.
        - Add Andre's reviewed-by
---
 xen/include/asm-arm/processor.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

Comments

Stefano Stabellini Sept. 15, 2017, 11:58 p.m. UTC | #1 
On Tue, 12 Sep 2017, Julien Grall wrote:
> FnV (FAR not Valid) bit was introduced by ARMv8 in both AArch32 and
> AArch64 (See D7-2275, D7-2277, G6-4958, G6-4962 in ARM DDI 0487B.a).
> 
> Note the new revision of ARMv8 defined more bits in HSR. They haven't
> been added at the moment because we have no use of them in Xen.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Stefano Stabellini <sstabellini@kernel.org>


> ---
> 
>     Changes in v2:
>         - Expand the commit message to explain why the other bits have
>         not been added.
>         - Add Andre's reviewed-by
> ---
>  xen/include/asm-arm/processor.h | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index bea4a56190..b6432b6bf4 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -587,7 +587,8 @@ union hsr {
>          unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
>          unsigned long res1:1;  /* RES0 */
>          unsigned long eat:1;   /* External abort type */
> -        unsigned long res2:15;
> +        unsigned long fnv:1;   /* FAR not Valid */
> +        unsigned long res2:14;
>          unsigned long len:1;   /* Instruction length */
>          unsigned long ec:6;    /* Exception Class */
>      } iabt; /* HSR_EC_INSTR_ABORT_* */
> @@ -598,10 +599,11 @@ union hsr {
>          unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
>          unsigned long cache:1; /* Cache Maintenance */
>          unsigned long eat:1;   /* External Abort Type */
> +        unsigned long fnv:1;   /* FAR not Valid */
>  #ifdef CONFIG_ARM_32
> -        unsigned long sbzp0:6;
> +        unsigned long sbzp0:5;
>  #else
> -        unsigned long sbzp0:4;
> +        unsigned long sbzp0:3;
>          unsigned long ar:1;    /* Acquire Release */
>          unsigned long sf:1;    /* Sixty Four bit register */
>  #endif
> -- 
> 2.11.0
>
diff mbox

Patch

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index bea4a56190..b6432b6bf4 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -587,7 +587,8 @@  union hsr {
         unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
         unsigned long res1:1;  /* RES0 */
         unsigned long eat:1;   /* External abort type */
-        unsigned long res2:15;
+        unsigned long fnv:1;   /* FAR not Valid */
+        unsigned long res2:14;
         unsigned long len:1;   /* Instruction length */
         unsigned long ec:6;    /* Exception Class */
     } iabt; /* HSR_EC_INSTR_ABORT_* */
@@ -598,10 +599,11 @@  union hsr {
         unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
         unsigned long cache:1; /* Cache Maintenance */
         unsigned long eat:1;   /* External Abort Type */
+        unsigned long fnv:1;   /* FAR not Valid */
 #ifdef CONFIG_ARM_32
-        unsigned long sbzp0:6;
+        unsigned long sbzp0:5;
 #else
-        unsigned long sbzp0:4;
+        unsigned long sbzp0:3;
         unsigned long ar:1;    /* Acquire Release */
         unsigned long sf:1;    /* Sixty Four bit register */
 #endif