From patchwork Mon Oct 2 17:31:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 9981051 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D85EC60384 for ; Mon, 2 Oct 2017 17:34:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C3DCC25D9E for ; Mon, 2 Oct 2017 17:34:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B797726CFF; Mon, 2 Oct 2017 17:34:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6521825D9E for ; Mon, 2 Oct 2017 17:34:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dz4ZX-0003ZK-Cn; Mon, 02 Oct 2017 17:32:03 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dz4ZV-0003Ys-Ma for xen-devel@lists.xen.org; Mon, 02 Oct 2017 17:32:01 +0000 Received: from [85.158.137.68] by server-3.bemta-3.messagelabs.com id 29/10-02046-01872D95; Mon, 02 Oct 2017 17:32:00 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRWlGSWpSXmKPExsVysyfVTVeg4lK kwcpmfoslHxezODB6HN39mymAMYo1My8pvyKBNWPlxUmsBadFKtZfeczWwNgm0MXIxSEksJlR 4v3bFqYuRk4g5zSjxNG5QiA2m4CmxJ3Pn8DiIgLSEtc+X2YEsZkFIiUOf/jBDmILC3hKNFxvB rNZBFQl/mydxgxi8wpYSPzZ8B6sXkJAXmJX20VWEJtTwFLi9pNDzBC7LCROv57BNIGRewEjwy pGjeLUorLUIl1DQ72kosz0jJLcxMwcXUMDY73c1OLixPTUnMSkYr3k/NxNjED/MgDBDsbVv50 OMUpyMCmJ8nrnX4oU4kvKT6nMSCzOiC8qzUktPsQow8GhJMF7vQwoJ1iUmp5akZaZAww0mLQE B4+SCO89kDRvcUFibnFmOkTqFKMuR8fNu3+YhFjy8vNSpcR5jcqBigRAijJK8+BGwIL+EqOsl DAvI9BRQjwFqUW5mSWo8q8YxTkYlYR5/4Cs4snMK4Hb9AroCCagI+Z0XQA5oiQRISXVwDifa/ UHR481MQcCRBIkDr6p1561uGrjR/skHr9jCfHhckd4ij/X6l4LcWdV/BtovHvWm9+NqndF8zO m6MxJ5bfTvsG2NFMhvs6ZaXNAmdJ7w9Olwr9vHRA4tIldVakmmFWuqnLK7iUL9yVKOC1stOSy W/6SY2Ndpd3DZ8armBuPM5mG/2R2UmIpzkg01GIuKk4EAJKAMVF1AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-3.tower-31.messagelabs.com!1506965519!117534550!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 19765 invoked from network); 2 Oct 2017 17:32:00 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-31.messagelabs.com with SMTP; 2 Oct 2017 17:32:00 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7614F1529; Mon, 2 Oct 2017 10:31:59 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8AB8F3F483; Mon, 2 Oct 2017 10:31:58 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 2 Oct 2017 18:31:43 +0100 Message-Id: <20171002173150.5404-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002173150.5404-1-julien.grall@arm.com> References: <20171002173150.5404-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v3 2/9] xen/arm: page: Clean-up the definition of MAIRVAL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently MAIRVAL is defined in term of MAIR0VAL and MAIR1VAL which are both hardcoded value. This makes quite difficult to understand the value written in both registers. Rework the definition by using value of each attribute shifted by their associated index. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - s/above/below/ in the comment - Add Stefano's reviewed-by Changes in v2: - Move this patch after "xen/arm: page: Use ARMv8 naming to improve readability" --- xen/include/asm-arm/page.h | 42 +++++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 3d0bc6db81..0ae1a2587b 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -22,6 +22,21 @@ #define LPAE_SH_INNER 0x3 /* + * Attribute Indexes. + * + * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page + * table entry. They are indexes into the bytes of the MAIR* + * registers, as defined below. + * + */ +#define MT_DEVICE_nGnRnE 0x0 +#define MT_NORMAL_NC 0x1 +#define MT_NORMAL_WT 0x2 +#define MT_NORMAL_WB 0x3 +#define MT_DEVICE_nGnRE 0x4 +#define MT_NORMAL 0x7 + +/* * LPAE Memory region attributes. Indexed by the AttrIndex bits of a * LPAE entry; the 8-bit fields are packed little-endian into MAIR0 and MAIR1. * @@ -38,24 +53,17 @@ * reserved 110 * MT_NORMAL 111 1111 1111 -- Write-back write-allocate */ -#define MAIR0VAL 0xeeaa4400 -#define MAIR1VAL 0xff000004 -#define MAIRVAL (MAIR0VAL|MAIR1VAL<<32) +#define MAIR(attr, mt) (_AC(attr, ULL) << ((mt) * 8)) -/* - * Attribute Indexes. - * - * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page - * table entry. They are indexes into the bytes of the MAIR* - * registers, as defined above. - * - */ -#define MT_DEVICE_nGnRnE 0x0 -#define MT_NORMAL_NC 0x1 -#define MT_NORMAL_WT 0x2 -#define MT_NORMAL_WB 0x3 -#define MT_DEVICE_nGnRE 0x4 -#define MT_NORMAL 0x7 +#define MAIRVAL (MAIR(0x00, MT_DEVICE_nGnRnE)| \ + MAIR(0x44, MT_NORMAL_NC) | \ + MAIR(0xaa, MT_NORMAL_WT) | \ + MAIR(0xee, MT_NORMAL_WB) | \ + MAIR(0x04, MT_DEVICE_nGnRE) | \ + MAIR(0xff, MT_NORMAL)) + +#define MAIR0VAL (MAIRVAL & 0xffffffff) +#define MAIR1VAL (MAIRVAL >> 32) #define PAGE_HYPERVISOR (MT_NORMAL) #define PAGE_HYPERVISOR_NOCACHE (MT_DEVICE_nGnRE)