From patchwork Mon Oct 9 13:23:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 9993225 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5E454602D7 for ; Mon, 9 Oct 2017 13:26:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4FD79287E9 for ; Mon, 9 Oct 2017 13:26:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 44D85287EA; Mon, 9 Oct 2017 13:26:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BC84C287DA for ; Mon, 9 Oct 2017 13:26:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e1Y2K-000811-Iz; Mon, 09 Oct 2017 13:24:00 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e1Y2J-00080T-7p for xen-devel@lists.xen.org; Mon, 09 Oct 2017 13:23:59 +0000 Received: from [85.158.139.211] by server-9.bemta-5.messagelabs.com id 06/94-02040-E687BD95; Mon, 09 Oct 2017 13:23:58 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTTe34na kwdtmC4slHxezODB6HN39mymAMYo1My8pvyKBNWPvym3sBe+EKg5vv8vcwPiAv4uRi0NIYDOj ROvZCewQzmlGiS2brrJ0MXJysAloStz5/IkJxBYRkJa49vkyI4jNLBApcfjDD3YQW1jARWLzt 71gNouAqsSqx3fAangFLCT6t+xgBrElBOQldrVdZAWxOQUsJaZtng4WFwKqufxhB+sERu4FjA yrGDWKU4vKUot0jSz0kooy0zNKchMzc3QNDUz1clOLixPTU3MSk4r1kvNzNzECPVzPwMC4g7F vld8hRkkOJiVR3ikFtyOF+JLyUyozEosz4otKc1KLDzHKcHAoSfB+LQfKCRalpqdWpGXmAEMN Ji3BwaMkwhsKkuYtLkjMLc5Mh0idYtTl6Lh59w+TEEtefl6qlDjvcZAiAZCijNI8uBGwsL/EK CslzMvIwMAgxFOQWpSbWYIq/4pRnINRSZj3UxnQFJ7MvBK4Ta+AjmACOoKx+AbIESWJCCmpBs bEqhl+qlfYQ+Yq3zz5/oHCrs4Sz2KVL4m+awrflTV+S1fYY3P+shCzFpeghXRsUnBxoPsvk67 zrzvPhof9FD02jfFEoHb7t7y73MInzksZsd99nTNfee2W10/3BN7tOPpdamb/ioqjtdxbi2sX 3NXwvLP0wuJ4leUXlW4/PXib4bYj11/r6CVKLMUZiYZazEXFiQDPDElgdgIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-13.tower-206.messagelabs.com!1507555437!90638675!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 39245 invoked from network); 9 Oct 2017 13:23:57 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-206.messagelabs.com with SMTP; 9 Oct 2017 13:23:57 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2234B15AD; Mon, 9 Oct 2017 06:23:57 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 36B713F578; Mon, 9 Oct 2017 06:23:56 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 9 Oct 2017 14:23:39 +0100 Message-Id: <20171009132341.1678-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132341.1678-1-julien.grall@arm.com> References: <20171009132341.1678-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v4 08/10] xen/arm: mm: Embed permission in the flags X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently, it is not possible to specify the permission of a new mapping. It would be necessary to use the function modify_xen_mappings with a different set of flags. Introduce a couple of new flags for the permissions (Non-eXecutable, Read-Only) and also provides definition that combine the memory attribute and permission for common combinations. PAGE_HYPERVISOR is now an alias to PAGE_HYPERVISOR_RW (read-write, non-executable mappings). This does not affect the current mapping using PAGE_HYPERVISOR because Xen is currently forcing all the mapping to be non-executable by default (see mfn_to_xen_entry). A follow-up patch will change modify_xen_mappings to use the new flags. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Add a comment about _PAGE_DEVICE and _PAGE_NORMAL Changes in v2: - Update the commit message --- xen/include/asm-arm/page.h | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index aa3e83f5b4..e2b3e402d0 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -69,12 +69,31 @@ * Layout of the flags used for updating the hypervisor page tables * * [0:2] Memory Attribute Index + * [3:4] Permission flags */ #define PAGE_AI_MASK(x) ((x) & 0x7U) -#define PAGE_HYPERVISOR (MT_NORMAL) -#define PAGE_HYPERVISOR_NOCACHE (MT_DEVICE_nGnRE) -#define PAGE_HYPERVISOR_WC (MT_NORMAL_NC) +#define _PAGE_XN_BIT 3 +#define _PAGE_RO_BIT 4 +#define _PAGE_XN (1U << _PAGE_XN_BIT) +#define _PAGE_RO (1U << _PAGE_RO_BIT) +#define PAGE_XN_MASK(x) (((x) >> _PAGE_XN_BIT) & 0x1U) +#define PAGE_RO_MASK(x) (((x) >> _PAGE_RO_BIT) & 0x1U) + +/* + * _PAGE_DEVICE and _PAGE_NORMAL are conveniences defines. They are not + * meant to be used outside of the headers. + */ +#define _PAGE_DEVICE _PAGE_XN +#define _PAGE_NORMAL MT_NORMAL + +#define PAGE_HYPERVISOR_RO (_PAGE_NORMAL|_PAGE_RO|_PAGE_XN) +#define PAGE_HYPERVISOR_RX (_PAGE_NORMAL|_PAGE_RO) +#define PAGE_HYPERVISOR_RW (_PAGE_NORMAL|_PAGE_XN) + +#define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW +#define PAGE_HYPERVISOR_NOCACHE (_PAGE_DEVICE|MT_DEVICE_nGnRE) +#define PAGE_HYPERVISOR_WC (_PAGE_DEVICE|MT_NORMAL_NC) /* * Defines for changing the hypervisor PTE .ro and .nx bits. This is only to be