From patchwork Thu Mar 28 15:04:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Woods, Brian" X-Patchwork-Id: 10875099 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C9F1F186E for ; Thu, 28 Mar 2019 15:07:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B373828565 for ; Thu, 28 Mar 2019 15:07:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A752E28AB8; Thu, 28 Mar 2019 15:07:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 37F6528565 for ; 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Thu, 28 Mar 2019 15:04:54 +0000 Received: from MWHPR12MB1597.namprd12.prod.outlook.com ([fe80::d8d0:f630:f358:d1a8]) by MWHPR12MB1597.namprd12.prod.outlook.com ([fe80::d8d0:f630:f358:d1a8%9]) with mapi id 15.20.1730.019; Thu, 28 Mar 2019 15:04:54 +0000 From: "Woods, Brian" To: "xen-devel@lists.xen.org" Thread-Topic: [PATCH v2 1/3] mwait-idle: add support for using halt Thread-Index: AQHU5XeZQOYGihi64UuNi/EebXFZig== Date: Thu, 28 Mar 2019 15:04:54 +0000 Message-ID: <20190328150426.7295-2-brian.woods@amd.com> References: <20190328150426.7295-1-brian.woods@amd.com> In-Reply-To: <20190328150426.7295-1-brian.woods@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN1PR12CA0048.namprd12.prod.outlook.com (2603:10b6:802:20::19) To MWHPR12MB1597.namprd12.prod.outlook.com (2603:10b6:301:10::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Brian.Woods@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.11.0 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cd60cbcf-0962-4eb6-7e84-08d6b38ebbd0 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: qm75stcWmRZZ0O3MvV+oDunv7yE/I9eWQROZ+EdVp36uoaZTGgST3StU4v0OFdV09lVOFQDnj9FiIvhICkWSV1wk09YRy3eZlhsAUB9XxuUEBdDJFFHSduRAwKpbZ2Z9rIQbfejOuyHVi0h+ZxGpwErsJxNw09Lv5+mxBK4VAjSmTw4xXh5llSBUmJlPuoQX7Gq0eQbVSOx1FJsm++9lOKm/Yiz9Emwx+6znk5exdY08JTc+eqpov+9aTi1M+suKkDejhz5f1ih5g9ajjglVU2bN0MCNC9HFoRgjag4H1OEXhK52bDcRKwiiECejoqxBfr9rir8vgLw9MnZyjhvBodIOF0t9FWvlcVVYq43Sxg4pyBQu+fq7Tz1rF7E4xSgaYSOHgib07ZuvJ6PhrDG4EoTigK0qWipufvTQukXXKks= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: cd60cbcf-0962-4eb6-7e84-08d6b38ebbd0 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Mar 2019 15:04:54.1989 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1709 Subject: [Xen-devel] [PATCH v2 1/3] mwait-idle: add support for using halt X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , "Woods, Brian" , Jan Beulich , =?iso-8859-1?q?Roger_Pau_Monn=E9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Brian Woods Some AMD processors can use a mixture of mwait and halt for accessing various c-states. In preparation for adding support for AMD processors, update the mwait-idle driver to optionally use halt. Signed-off-by: Brian Woods --- xen/arch/x86/acpi/cpu_idle.c | 2 +- xen/arch/x86/cpu/mwait-idle.c | 19 +++++++++++++------ xen/include/asm-x86/cpuidle.h | 1 + 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 654de24f40..b45824d343 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -439,7 +439,7 @@ static void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx) mwait_idle_with_hints(cx->address, MWAIT_ECX_INTERRUPT_BREAK); } -static void acpi_idle_do_entry(struct acpi_processor_cx *cx) +void acpi_idle_do_entry(struct acpi_processor_cx *cx) { struct cpu_info *info = get_cpu_info(); diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index f89c52f256..b9c7f75882 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -103,6 +103,11 @@ static const struct cpuidle_state { #define CPUIDLE_FLAG_DISABLED 0x1 /* + * On certain AMD families that support mwait, only c1 can be reached by + * mwait and to reach c2, halt has to be used. + */ +#define CPUIDLE_FLAG_USE_HALT 0x2 +/* * Set this flag for states where the HW flushes the TLB for us * and so we don't need cross-calls to keep it consistent. * If this flag is set, SW flushes the TLB, so even if the @@ -784,7 +789,7 @@ static void mwait_idle(void) update_last_cx_stat(power, cx, before); if (cpu_is_haltable(cpu)) - mwait_idle_with_hints(eax, MWAIT_ECX_INTERRUPT_BREAK); + acpi_idle_do_entry(cx); after = cpuidle_get_tick(); @@ -1184,8 +1189,9 @@ static int mwait_idle_cpu_init(struct notifier_block *nfb, for (cstate = 0; cpuidle_state_table[cstate].target_residency; ++cstate) { unsigned int num_substates, hint, state; struct acpi_processor_cx *cx; + const unsigned int cflags = cpuidle_state_table[cstate].flags; - hint = flg2MWAIT(cpuidle_state_table[cstate].flags); + hint = flg2MWAIT(cflags); state = MWAIT_HINT2CSTATE(hint) + 1; if (state > max_cstate) { @@ -1196,13 +1202,13 @@ static int mwait_idle_cpu_init(struct notifier_block *nfb, /* Number of sub-states for this state in CPUID.MWAIT. */ num_substates = (mwait_substates >> (state * 4)) & MWAIT_SUBSTATE_MASK; + /* If NO sub-states for this state in CPUID, skip it. */ - if (num_substates == 0) + if (num_substates == 0 && !(cflags & CPUIDLE_FLAG_USE_HALT)) continue; /* if state marked as disabled, skip it */ - if (cpuidle_state_table[cstate].flags & - CPUIDLE_FLAG_DISABLED) { + if (cflags & CPUIDLE_FLAG_DISABLED) { printk(XENLOG_DEBUG PREFIX "state %s is disabled", cpuidle_state_table[cstate].name); continue; @@ -1221,7 +1227,8 @@ static int mwait_idle_cpu_init(struct notifier_block *nfb, cx = dev->states + dev->count; cx->type = state; cx->address = hint; - cx->entry_method = ACPI_CSTATE_EM_FFH; + cx->entry_method = cflags & CPUIDLE_FLAG_USE_HALT ? + ACPI_CSTATE_EM_HALT : ACPI_CSTATE_EM_FFH; cx->latency = cpuidle_state_table[cstate].exit_latency; cx->target_residency = cpuidle_state_table[cstate].target_residency; diff --git a/xen/include/asm-x86/cpuidle.h b/xen/include/asm-x86/cpuidle.h index 08da01803f..33c8cf1593 100644 --- a/xen/include/asm-x86/cpuidle.h +++ b/xen/include/asm-x86/cpuidle.h @@ -18,6 +18,7 @@ extern uint64_t (*cpuidle_get_tick)(void); int mwait_idle_init(struct notifier_block *); int cpuidle_init_cpu(unsigned int cpu); +void acpi_idle_do_entry(struct acpi_processor_cx *cx); void default_dead_idle(void); void acpi_dead_idle(void); void trace_exit_reason(u32 *irq_traced);