From patchwork Thu Mar 28 15:04:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Woods, Brian" X-Patchwork-Id: 10875095 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8A571390 for ; Thu, 28 Mar 2019 15:06:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D310E28AB8 for ; Thu, 28 Mar 2019 15:06:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C6C3928D17; Thu, 28 Mar 2019 15:06:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 645D528AB8 for ; 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Thu, 28 Mar 2019 15:04:58 +0000 Received: from MWHPR12MB1597.namprd12.prod.outlook.com ([fe80::d8d0:f630:f358:d1a8]) by MWHPR12MB1597.namprd12.prod.outlook.com ([fe80::d8d0:f630:f358:d1a8%9]) with mapi id 15.20.1730.019; Thu, 28 Mar 2019 15:04:58 +0000 From: "Woods, Brian" To: "xen-devel@lists.xen.org" Thread-Topic: [PATCH v2 2/3] mwait-idle: add support for AMD processors Thread-Index: AQHU5XecjZm2W8agMECWgwx39HNo0w== Date: Thu, 28 Mar 2019 15:04:58 +0000 Message-ID: <20190328150426.7295-3-brian.woods@amd.com> References: <20190328150426.7295-1-brian.woods@amd.com> In-Reply-To: <20190328150426.7295-1-brian.woods@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN1PR12CA0048.namprd12.prod.outlook.com (2603:10b6:802:20::19) To MWHPR12MB1597.namprd12.prod.outlook.com (2603:10b6:301:10::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Brian.Woods@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.11.0 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 464d6c5d-ba3c-4a44-0d45-08d6b38ebe5d x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: /bCA9RI+4h6BKRJrGr5Hm09PmbUiXbNZShwaDc6PBGlczlE4H1NEJXcqdIFyzTRmi9vboANncV3XStk8rXJ+6R2KIomy8rZo34zXRoGqT7zQ9dnZOb1UGAOcuWBFtcCkH5fQV0h1UL7vPvPcM2b4m9bABuOniZ/RWc6pn1M5m/9SN1tUWhZ99MT9dy2Bstr2z2PYHJ+pNpiwBgeSCYO9NziHzvkbA6ky/E5pPeTUkCYkKfIbb/ZtqGy/oN0BEsrmgdXx3TkBDLU3VaYrPTxX3/RjLKZ4BUjwy5Okr/9F4FjA9tY2eL3hcqLTXUenkS2zPeWeGwm2reB5iXjFuoy9Ar/RiIJUI8dEOONVqgPG+UZvvg9ePGYLqTDVGi74zw8UCNZcDsKWiiNqZYDJx20zpY/I3orv92Glyzf5tu0z2cc= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 464d6c5d-ba3c-4a44-0d45-08d6b38ebe5d X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Mar 2019 15:04:58.3734 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1454 Subject: [Xen-devel] [PATCH v2 2/3] mwait-idle: add support for AMD processors X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , "Woods, Brian" , Jan Beulich , =?iso-8859-1?q?Roger_Pau_Monn=E9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Brian Woods Newer AMD processors (F17h) have mwait support which is compatible with Intel. Add some checks to make sure vendor specific code is run correctly and some infrastructure to facilitate adding AMD processors. This is done so that Xen will not be reliant on dom0 passing the parsed ACPI tables back since Xen doesn't have an AML interpreter. This can be unreliable or broken in some cases. Signed-off-by: Brian Woods --- xen/arch/x86/cpu/mwait-idle.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index b9c7f75882..58629f1c29 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -964,6 +964,13 @@ static const struct x86_cpu_id intel_idle_ids[] __initconstrel = { {} }; +#define ACPU(family, model, cpu) \ + { X86_VENDOR_AMD, family, model, X86_FEATURE_ALWAYS, &idle_cpu_##cpu} + +static const struct x86_cpu_id amd_idle_ids[] __initconstrel = { + {} +}; + /* * ivt_idle_state_table_update(void) * @@ -1100,6 +1107,9 @@ static void __init sklh_idle_state_table_update(void) */ static void __init mwait_idle_state_table_update(void) { + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) + return; + switch (boot_cpu_data.x86_model) { case 0x3e: /* IVT */ ivt_idle_state_table_update(); @@ -1117,7 +1127,16 @@ static void __init mwait_idle_state_table_update(void) static int __init mwait_idle_probe(void) { unsigned int eax, ebx, ecx; - const struct x86_cpu_id *id = x86_match_cpu(intel_idle_ids); + const struct x86_cpu_id *id = NULL; + + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + id = x86_match_cpu(intel_idle_ids); + break; + case X86_VENDOR_AMD: + id = x86_match_cpu(amd_idle_ids); + break; + } if (!id) { pr_debug(PREFIX "does not run on family %d model %d\n",