| Message ID | 20190508161603.21964-4-julien.grall@arm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | xen/arm: TLB flush helpers rework | expand |
On Wed, 8 May 2019, Julien Grall wrote: > TLB helpers in the headers tlbflush.h are currently quite confusing to > use the name may lead to think they are dealing with hypervisors TLBs > while they actually deal with guest TLBs. > > Rename them to make it clearer that we are dealing with guest TLBs. > > Signed-off-by: Julien Grall <julien.grall@arm.com> > Reviewed-by: Andrii Anisov <andrii_anisov@epam.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in v2: > - Add Andrii's reviewed-by > --- > xen/arch/arm/p2m.c | 6 +++--- > xen/arch/arm/smp.c | 2 +- > xen/arch/arm/traps.c | 2 +- > xen/include/asm-arm/arm32/flushtlb.h | 8 ++++---- > xen/include/asm-arm/arm64/flushtlb.h | 8 ++++---- > 5 files changed, 13 insertions(+), 13 deletions(-) > > diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c > index c38bd7e16e..92c2413f20 100644 > --- a/xen/arch/arm/p2m.c > +++ b/xen/arch/arm/p2m.c > @@ -151,7 +151,7 @@ void p2m_restore_state(struct vcpu *n) > * when running multiple vCPU of the same domain on a single pCPU. > */ > if ( *last_vcpu_ran != INVALID_VCPU_ID && *last_vcpu_ran != n->vcpu_id ) > - flush_tlb_local(); > + flush_guest_tlb_local(); > > *last_vcpu_ran = n->vcpu_id; > } > @@ -196,7 +196,7 @@ static void p2m_force_tlb_flush_sync(struct p2m_domain *p2m) > isb(); > } > > - flush_tlb(); > + flush_guest_tlb(); > > if ( ovttbr != READ_SYSREG64(VTTBR_EL2) ) > { > @@ -1969,7 +1969,7 @@ static void setup_virt_paging_one(void *data) > WRITE_SYSREG(READ_SYSREG(HCR_EL2) | HCR_VM, HCR_EL2); > isb(); > > - flush_tlb_all_local(); > + flush_all_guests_tlb_local(); > } > } > > diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c > index 62f57f0ba2..ce1fcc8ef9 100644 > --- a/xen/arch/arm/smp.c > +++ b/xen/arch/arm/smp.c > @@ -8,7 +8,7 @@ > void flush_tlb_mask(const cpumask_t *mask) > { > /* No need to IPI other processors on ARM, the processor takes care of it. */ > - flush_tlb_all(); > + flush_all_guests_tlb(); > } > > void smp_send_event_check_mask(const cpumask_t *mask) > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index d8b9a8a0f0..1aba970415 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -1924,7 +1924,7 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, > * still be inaccurate. > */ > if ( !is_data ) > - flush_tlb_local(); > + flush_guest_tlb_local(); > > rc = gva_to_ipa(gva, &gpa, GV2M_READ); > /* > diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h > index bbcc82f490..22e100eccf 100644 > --- a/xen/include/asm-arm/arm32/flushtlb.h > +++ b/xen/include/asm-arm/arm32/flushtlb.h > @@ -2,7 +2,7 @@ > #define __ASM_ARM_ARM32_FLUSHTLB_H__ > > /* Flush local TLBs, current VMID only */ > -static inline void flush_tlb_local(void) > +static inline void flush_guest_tlb_local(void) > { > dsb(sy); > > @@ -13,7 +13,7 @@ static inline void flush_tlb_local(void) > } > > /* Flush inner shareable TLBs, current VMID only */ > -static inline void flush_tlb(void) > +static inline void flush_guest_tlb(void) > { > dsb(sy); > > @@ -24,7 +24,7 @@ static inline void flush_tlb(void) > } > > /* Flush local TLBs, all VMIDs, non-hypervisor mode */ > -static inline void flush_tlb_all_local(void) > +static inline void flush_all_guests_tlb_local(void) > { > dsb(sy); > > @@ -35,7 +35,7 @@ static inline void flush_tlb_all_local(void) > } > > /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ > -static inline void flush_tlb_all(void) > +static inline void flush_all_guests_tlb(void) > { > dsb(sy); > > diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h > index 942f2d3992..adbbd5c522 100644 > --- a/xen/include/asm-arm/arm64/flushtlb.h > +++ b/xen/include/asm-arm/arm64/flushtlb.h > @@ -2,7 +2,7 @@ > #define __ASM_ARM_ARM64_FLUSHTLB_H__ > > /* Flush local TLBs, current VMID only */ > -static inline void flush_tlb_local(void) > +static inline void flush_guest_tlb_local(void) > { > asm volatile( > "dsb sy;" > @@ -13,7 +13,7 @@ static inline void flush_tlb_local(void) > } > > /* Flush innershareable TLBs, current VMID only */ > -static inline void flush_tlb(void) > +static inline void flush_guest_tlb(void) > { > asm volatile( > "dsb sy;" > @@ -24,7 +24,7 @@ static inline void flush_tlb(void) > } > > /* Flush local TLBs, all VMIDs, non-hypervisor mode */ > -static inline void flush_tlb_all_local(void) > +static inline void flush_all_guests_tlb_local(void) > { > asm volatile( > "dsb sy;" > @@ -35,7 +35,7 @@ static inline void flush_tlb_all_local(void) > } > > /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ > -static inline void flush_tlb_all(void) > +static inline void flush_all_guests_tlb(void) > { > asm volatile( > "dsb sy;" > -- > 2.11.0 >
diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index c38bd7e16e..92c2413f20 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -151,7 +151,7 @@ void p2m_restore_state(struct vcpu *n) * when running multiple vCPU of the same domain on a single pCPU. */ if ( *last_vcpu_ran != INVALID_VCPU_ID && *last_vcpu_ran != n->vcpu_id ) - flush_tlb_local(); + flush_guest_tlb_local(); *last_vcpu_ran = n->vcpu_id; } @@ -196,7 +196,7 @@ static void p2m_force_tlb_flush_sync(struct p2m_domain *p2m) isb(); } - flush_tlb(); + flush_guest_tlb(); if ( ovttbr != READ_SYSREG64(VTTBR_EL2) ) { @@ -1969,7 +1969,7 @@ static void setup_virt_paging_one(void *data) WRITE_SYSREG(READ_SYSREG(HCR_EL2) | HCR_VM, HCR_EL2); isb(); - flush_tlb_all_local(); + flush_all_guests_tlb_local(); } } diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index 62f57f0ba2..ce1fcc8ef9 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -8,7 +8,7 @@ void flush_tlb_mask(const cpumask_t *mask) { /* No need to IPI other processors on ARM, the processor takes care of it. */ - flush_tlb_all(); + flush_all_guests_tlb(); } void smp_send_event_check_mask(const cpumask_t *mask) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index d8b9a8a0f0..1aba970415 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1924,7 +1924,7 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, * still be inaccurate. */ if ( !is_data ) - flush_tlb_local(); + flush_guest_tlb_local(); rc = gva_to_ipa(gva, &gpa, GV2M_READ); /* diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h index bbcc82f490..22e100eccf 100644 --- a/xen/include/asm-arm/arm32/flushtlb.h +++ b/xen/include/asm-arm/arm32/flushtlb.h @@ -2,7 +2,7 @@ #define __ASM_ARM_ARM32_FLUSHTLB_H__ /* Flush local TLBs, current VMID only */ -static inline void flush_tlb_local(void) +static inline void flush_guest_tlb_local(void) { dsb(sy); @@ -13,7 +13,7 @@ static inline void flush_tlb_local(void) } /* Flush inner shareable TLBs, current VMID only */ -static inline void flush_tlb(void) +static inline void flush_guest_tlb(void) { dsb(sy); @@ -24,7 +24,7 @@ static inline void flush_tlb(void) } /* Flush local TLBs, all VMIDs, non-hypervisor mode */ -static inline void flush_tlb_all_local(void) +static inline void flush_all_guests_tlb_local(void) { dsb(sy); @@ -35,7 +35,7 @@ static inline void flush_tlb_all_local(void) } /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ -static inline void flush_tlb_all(void) +static inline void flush_all_guests_tlb(void) { dsb(sy); diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h index 942f2d3992..adbbd5c522 100644 --- a/xen/include/asm-arm/arm64/flushtlb.h +++ b/xen/include/asm-arm/arm64/flushtlb.h @@ -2,7 +2,7 @@ #define __ASM_ARM_ARM64_FLUSHTLB_H__ /* Flush local TLBs, current VMID only */ -static inline void flush_tlb_local(void) +static inline void flush_guest_tlb_local(void) { asm volatile( "dsb sy;" @@ -13,7 +13,7 @@ static inline void flush_tlb_local(void) } /* Flush innershareable TLBs, current VMID only */ -static inline void flush_tlb(void) +static inline void flush_guest_tlb(void) { asm volatile( "dsb sy;" @@ -24,7 +24,7 @@ static inline void flush_tlb(void) } /* Flush local TLBs, all VMIDs, non-hypervisor mode */ -static inline void flush_tlb_all_local(void) +static inline void flush_all_guests_tlb_local(void) { asm volatile( "dsb sy;" @@ -35,7 +35,7 @@ static inline void flush_tlb_all_local(void) } /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ -static inline void flush_tlb_all(void) +static inline void flush_all_guests_tlb(void) { asm volatile( "dsb sy;"