| Message ID | 20190607092232.83179-13-roger.pau@citrix.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | pci: expand usage of pci_sbdf_t | expand |
>>> On 07.06.19 at 11:22, <roger.pau@citrix.com> wrote: > This reduces the number of parameters of the function to two, and > simplifies some of the calling sites. > > Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
On Fri, Jun 07, 2019 at 11:22:31AM +0200, Roger Pau Monne wrote: > This reduces the number of parameters of the function to two, and > simplifies some of the calling sites. > > Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> As far as AMD IOMMU Acked-by: Brian Woods <brian.woods@amd.com > --- > Cc: Jan Beulich <jbeulich@suse.com> > Cc: Andrew Cooper <andrew.cooper3@citrix.com> > Cc: Wei Liu <wl@xen.org> > Cc: George Dunlap <George.Dunlap@eu.citrix.com> > Cc: Ian Jackson <ian.jackson@eu.citrix.com> > Cc: Julien Grall <julien.grall@arm.com> > Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> > Cc: Stefano Stabellini <sstabellini@kernel.org> > Cc: Tim Deegan <tim@xen.org> > Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> > Cc: Brian Woods <brian.woods@amd.com> > Cc: Kevin Tian <kevin.tian@intel.com> > --- > xen/arch/x86/cpu/amd.c | 4 ++-- > xen/arch/x86/msi.c | 12 ++++-------- > xen/arch/x86/oprofile/op_model_athlon.c | 4 +++- > xen/arch/x86/x86_64/pci.c | 17 ++++------------- > xen/drivers/char/ehci-dbgp.c | 5 +++-- > xen/drivers/char/ns16550.c | 22 ++++++++++++---------- > xen/drivers/passthrough/amd/iommu_init.c | 8 ++++---- > xen/drivers/passthrough/pci.c | 8 ++++---- > xen/drivers/passthrough/vtd/quirks.c | 8 ++++---- > xen/drivers/vpci/header.c | 7 +++---- > xen/drivers/vpci/vpci.c | 2 +- > xen/include/xen/pci.h | 4 +--- > 12 files changed, 45 insertions(+), 56 deletions(-) > > diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c > index 2e6529fba3..86273b6a07 100644 > --- a/xen/arch/x86/cpu/amd.c > +++ b/xen/arch/x86/cpu/amd.c > @@ -707,11 +707,11 @@ static void init_amd(struct cpuinfo_x86 *c) > (h & 0x1) ? "clearing D18F3x5C[0]" : ""); > > if (l & 0x1f) > - pci_conf_write32(0, 0, 0x18, 3, 0x58, > + pci_conf_write32(PCI_SBDF(0, 0, 0x18, 3), 0x58, > l & ~0x1f); > > if (h & 0x1) > - pci_conf_write32(0, 0, 0x18, 3, 0x5c, > + pci_conf_write32(PCI_SBDF(0, 0, 0x18, 3), 0x5c, > h & ~0x1); > } > > diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c > index cbc1e3b3f0..9a1ce33b42 100644 > --- a/xen/arch/x86/msi.c > +++ b/xen/arch/x86/msi.c > @@ -251,21 +251,17 @@ static int write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) > { > struct pci_dev *dev = entry->dev; > int pos = entry->msi_attrib.pos; > - u16 seg = dev->seg; > - u8 bus = dev->bus; > - u8 slot = PCI_SLOT(dev->devfn); > - u8 func = PCI_FUNC(dev->devfn); > int nr = entry->msi_attrib.entry_nr; > > ASSERT((msg->data & (entry[-nr].msi.nvec - 1)) == nr); > if ( nr ) > return 0; > > - pci_conf_write32(seg, bus, slot, func, msi_lower_address_reg(pos), > + pci_conf_write32(dev->sbdf, msi_lower_address_reg(pos), > msg->address_lo); > if ( entry->msi_attrib.is_64 ) > { > - pci_conf_write32(seg, bus, slot, func, msi_upper_address_reg(pos), > + pci_conf_write32(dev->sbdf, msi_upper_address_reg(pos), > msg->address_hi); > pci_conf_write16(dev->sbdf, msi_data_reg(pos, 1), msg->data); > } > @@ -395,7 +391,7 @@ static bool msi_set_mask_bit(struct irq_desc *desc, bool host, bool guest) > mask_bits = pci_conf_read32(pdev->sbdf, entry->msi.mpos); > mask_bits &= ~((u32)1 << entry->msi_attrib.entry_nr); > mask_bits |= (u32)flag << entry->msi_attrib.entry_nr; > - pci_conf_write32(seg, bus, slot, func, entry->msi.mpos, mask_bits); > + pci_conf_write32(pdev->sbdf, entry->msi.mpos, mask_bits); > } > break; > case PCI_CAP_ID_MSIX: > @@ -716,7 +712,7 @@ static int msi_capability_init(struct pci_dev *dev, > /* All MSIs are unmasked by default, Mask them all */ > maskbits = pci_conf_read32(dev->sbdf, mpos); > maskbits |= ~(u32)0 >> (32 - maxvec); > - pci_conf_write32(seg, bus, slot, func, mpos, maskbits); > + pci_conf_write32(dev->sbdf, mpos, maskbits); > } > list_add_tail(&entry->list, &dev->msi_list); > > diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofile/op_model_athlon.c > index 3bf0b0214d..5c48f868ae 100644 > --- a/xen/arch/x86/oprofile/op_model_athlon.c > +++ b/xen/arch/x86/oprofile/op_model_athlon.c > @@ -472,7 +472,9 @@ static int __init init_ibs_nmi(void) > if ((vendor_id == PCI_VENDOR_ID_AMD) && > (dev_id == PCI_DEVICE_ID_AMD_10H_NB_MISC)) { > > - pci_conf_write32(0, bus, dev, func, IBSCTL, > + pci_conf_write32( > + PCI_SBDF(0, bus, dev, func), > + IBSCTL, > IBSCTL_LVTOFFSETVAL | APIC_EILVT_LVTOFF_IBS); > > value = pci_conf_read32(PCI_SBDF(0, bus, dev, func), > diff --git a/xen/arch/x86/x86_64/pci.c b/xen/arch/x86/x86_64/pci.c > index f014fe0fc5..aad1c3f7cf 100644 > --- a/xen/arch/x86/x86_64/pci.c > +++ b/xen/arch/x86/x86_64/pci.c > @@ -66,19 +66,10 @@ void pci_conf_write16(pci_sbdf_t sbdf, unsigned int reg, uint16_t data) > pci_conf_write(PCI_CONF_ADDRESS(sbdf, reg), reg & 2, 2, data); > } > > -#undef PCI_CONF_ADDRESS > -#define PCI_CONF_ADDRESS(bus, dev, func, reg) \ > - (0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3)) > - > -void pci_conf_write32( > - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, > - unsigned int reg, uint32_t data) > +void pci_conf_write32(pci_sbdf_t sbdf, unsigned int reg, uint32_t data) > { > - if ( seg || reg > 255 ) > - pci_mmcfg_write(seg, bus, PCI_DEVFN(dev, func), reg, 4, data); > + if ( sbdf.seg || reg > 255 ) > + pci_mmcfg_write(sbdf.seg, sbdf.bus, sbdf.devfn, reg, 4, data); > else > - { > - BUG_ON((bus > 255) || (dev > 31) || (func > 7)); > - pci_conf_write(PCI_CONF_ADDRESS(bus, dev, func, reg), 0, 4, data); > - } > + pci_conf_write(PCI_CONF_ADDRESS(sbdf, reg), 0, 4, data); > } > diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c > index b780334953..b6e155d17b 100644 > --- a/xen/drivers/char/ehci-dbgp.c > +++ b/xen/drivers/char/ehci-dbgp.c > @@ -1012,7 +1012,8 @@ static void nvidia_set_debug_port(struct ehci_dbgp *dbgp, unsigned int port) > > dword &= ~(0x0f << 12); > dword |= (port & 0x0f) << 12; > - pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, 0x74, dword); > + pci_conf_write32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), 0x74, > + dword); > dbgp_printk("set debug port to %u\n", port); > } > > @@ -1436,7 +1437,7 @@ static void ehci_dbgp_resume(struct serial_port *port) > if ( !dbgp->ehci_debug ) > return; > > - pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, dbgp->bar, > + pci_conf_write32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), dbgp->bar, > dbgp->bar_val); > pci_conf_write16(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), > PCI_COMMAND, dbgp->pci_cr); > diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c > index 20eaecee59..e518f2d790 100644 > --- a/xen/drivers/char/ns16550.c > +++ b/xen/drivers/char/ns16550.c > @@ -630,7 +630,8 @@ static void pci_serial_early_init(struct ns16550 *uart) > (uart->io_base & 0xF000) | > ((uart->io_base & 0xF000) >> 8)); > > - pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], > + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], > + uart->ps_bdf[2]), > PCI_BASE_ADDRESS_0, > uart->io_base | PCI_BASE_ADDRESS_SPACE_IO); > pci_conf_write16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], > @@ -860,13 +861,14 @@ static void _ns16550_resume(struct serial_port *port) > > if ( uart->bar ) > { > - pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], > + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], > + uart->ps_bdf[2]), > PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->bar); > > /* If 64 bit BAR, write higher 32 bits to BAR+4 */ > if ( uart->bar & PCI_BASE_ADDRESS_MEM_TYPE_64 ) > - pci_conf_write32(0, uart->ps_bdf[0], > - uart->ps_bdf[1], uart->ps_bdf[2], > + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], > + uart->ps_bdf[2]), > PCI_BASE_ADDRESS_0 + (uart->bar_idx+1)*4, uart->bar64); > > pci_conf_write16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], > @@ -1121,11 +1123,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) > /* MMIO based */ > if ( param->mmio && !(bar & PCI_BASE_ADDRESS_SPACE_IO) ) > { > - pci_conf_write32(0, b, d, f, > + pci_conf_write32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); > len = pci_conf_read32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + bar_idx * 4); > - pci_conf_write32(0, b, d, f, > + pci_conf_write32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + bar_idx*4, bar); > > /* Handle 64 bit BAR if found */ > @@ -1133,11 +1135,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) > { > bar_64 = pci_conf_read32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + (bar_idx + 1) * 4); > - pci_conf_write32(0, b, d, f, > + pci_conf_write32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ~0u); > len_64 = pci_conf_read32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + (bar_idx + 1) * 4); > - pci_conf_write32(0, b, d, f, > + pci_conf_write32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, bar_64); > size = ((u64)~0 << 32) | PCI_BASE_ADDRESS_MEM_MASK; > size &= ((u64)len_64 << 32) | len; > @@ -1151,11 +1153,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) > /* IO based */ > else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO) ) > { > - pci_conf_write32(0, b, d, f, > + pci_conf_write32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); > len = pci_conf_read32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0); > - pci_conf_write32(0, b, d, f, > + pci_conf_write32(PCI_SBDF(0, b, d, f), > PCI_BASE_ADDRESS_0 + bar_idx*4, bar); > size = len & PCI_BASE_ADDRESS_IO_MASK; > > diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthrough/amd/iommu_init.c > index 6083d51b91..d19531493b 100644 > --- a/xen/drivers/passthrough/amd/iommu_init.c > +++ b/xen/drivers/passthrough/amd/iommu_init.c > @@ -843,22 +843,22 @@ static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) > (boot_cpu_data.x86_model > 0x1f) ) > return; > > - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90); > + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90); > value = pci_conf_read32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf4); > > if ( value & (1 << 2) ) > return; > > /* Select NB indirect register 0x90 and enable writing */ > - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90 | (1 << 8)); > + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90 | (1 << 8)); > > - pci_conf_write32(iommu->seg, bus, dev, func, 0xf4, value | (1 << 2)); > + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf4, value | (1 << 2)); > printk(XENLOG_INFO > "AMD-Vi: Applying erratum 746 workaround for IOMMU at %04x:%02x:%02x.%u\n", > iommu->seg, bus, dev, func); > > /* Clear the enable writing bit */ > - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90); > + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90); > } > > static void enable_iommu(struct amd_iommu *iommu) > diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c > index ff400e9a31..5271f8d69c 100644 > --- a/xen/drivers/passthrough/pci.c > +++ b/xen/drivers/passthrough/pci.c > @@ -638,7 +638,7 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned int pos, > ASSERT(!((flags & PCI_BAR_VF) && (flags & PCI_BAR_ROM))); > ASSERT((flags & PCI_BAR_ROM) || > (bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY); > - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos, ~0); > + pci_conf_write32(sbdf, pos, ~0); > if ( is64bits ) > { > if ( flags & PCI_BAR_LAST ) > @@ -651,17 +651,17 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned int pos, > return 1; > } > hi = pci_conf_read32(sbdf, pos + 4); > - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos + 4, ~0); > + pci_conf_write32(sbdf, pos + 4, ~0); > } > size = pci_conf_read32(sbdf, pos) & mask; > if ( is64bits ) > { > size |= (uint64_t)pci_conf_read32(sbdf, pos + 4) << 32; > - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos + 4, hi); > + pci_conf_write32(sbdf, pos + 4, hi); > } > else if ( size ) > size |= (uint64_t)~0 << 32; > - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos, bar); > + pci_conf_write32(sbdf, pos, bar); > size = -size; > > if ( paddr ) > diff --git a/xen/drivers/passthrough/vtd/quirks.c b/xen/drivers/passthrough/vtd/quirks.c > index 28e9597014..b6e2d313f0 100644 > --- a/xen/drivers/passthrough/vtd/quirks.c > +++ b/xen/drivers/passthrough/vtd/quirks.c > @@ -441,7 +441,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) > case 0x3728: /* Xeon C5500/C3500 (JasperForest) */ > case 0x3c28: /* Sandybridge */ > val = pci_conf_read32(pdev->sbdf, 0x1AC); > - pci_conf_write32(seg, bus, dev, func, 0x1AC, val | (1 << 31)); > + pci_conf_write32(pdev->sbdf, 0x1AC, val | (1 << 31)); > printk(XENLOG_INFO "Masked VT-d error signaling on %04x:%02x:%02x.%u\n", > seg, bus, dev, func); > break; > @@ -489,9 +489,9 @@ void pci_vtd_quirk(const struct pci_dev *pdev) > action = "Found masked"; > else if ( !ff ) > { > - pci_conf_write32(seg, bus, dev, func, pos + PCI_ERR_UNCOR_MASK, > + pci_conf_write32(pdev->sbdf, pos + PCI_ERR_UNCOR_MASK, > val | PCI_ERR_UNC_UNSUP); > - pci_conf_write32(seg, bus, dev, func, pos + PCI_ERR_COR_MASK, > + pci_conf_write32(pdev->sbdf, pos + PCI_ERR_COR_MASK, > val2 | PCI_ERR_COR_ADV_NFAT); > action = "Masked"; > } > @@ -500,7 +500,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) > > /* XPUNCERRMSK Send Completion with Unsupported Request */ > val = pci_conf_read32(pdev->sbdf, 0x20c); > - pci_conf_write32(seg, bus, dev, func, 0x20c, val | (1 << 4)); > + pci_conf_write32(pdev->sbdf, 0x20c, val | (1 << 4)); > > printk(XENLOG_INFO "%s UR signaling on %04x:%02x:%02x.%u\n", > action, seg, bus, dev, func); > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index f377e6abdf..3c794f486d 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -85,7 +85,6 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, > bool rom_only) > { > struct vpci_header *header = &pdev->vpci->header; > - uint8_t slot = PCI_SLOT(pdev->devfn), func = PCI_FUNC(pdev->devfn); > bool map = cmd & PCI_COMMAND_MEMORY; > unsigned int i; > > @@ -113,7 +112,7 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, > (map ? PCI_ROM_ADDRESS_ENABLE : 0); > > header->bars[i].enabled = header->rom_enabled = map; > - pci_conf_write32(pdev->seg, pdev->bus, slot, func, rom_pos, val); > + pci_conf_write32(pdev->sbdf, rom_pos, val); > return; > } > > @@ -395,7 +394,7 @@ static void bar_write(const struct pci_dev *pdev, unsigned int reg, > val |= bar->prefetchable ? PCI_BASE_ADDRESS_MEM_PREFETCH : 0; > } > > - pci_conf_write32(pdev->seg, pdev->bus, slot, func, reg, val); > + pci_conf_write32(pdev->sbdf, reg, val); > } > > static void rom_write(const struct pci_dev *pdev, unsigned int reg, > @@ -426,7 +425,7 @@ static void rom_write(const struct pci_dev *pdev, unsigned int reg, > { > /* Just update the ROM BAR field. */ > header->rom_enabled = new_enabled; > - pci_conf_write32(pdev->seg, pdev->bus, slot, func, reg, val); > + pci_conf_write32(pdev->sbdf, reg, val); > } > /* > * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note that > diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c > index b61672f295..ddbfa56489 100644 > --- a/xen/drivers/vpci/vpci.c > +++ b/xen/drivers/vpci/vpci.c > @@ -253,7 +253,7 @@ static void vpci_write_hw(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, > switch ( size ) > { > case 4: > - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, reg, data); > + pci_conf_write32(sbdf, reg, data); > break; > > case 3: > diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h > index cb90d2f785..e6af45cfe7 100644 > --- a/xen/include/xen/pci.h > +++ b/xen/include/xen/pci.h > @@ -177,9 +177,7 @@ uint16_t pci_conf_read16(pci_sbdf_t sbdf, unsigned int reg); > uint32_t pci_conf_read32(pci_sbdf_t sbdf, unsigned int reg); > void pci_conf_write8(pci_sbdf_t sbdf, unsigned int reg, uint8_t data); > void pci_conf_write16(pci_sbdf_t sbdf, unsigned int reg, uint16_t data); > -void pci_conf_write32( > - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, > - unsigned int reg, uint32_t data); > +void pci_conf_write32(pci_sbdf_t sbdf, unsigned int reg, uint32_t data); > uint32_t pci_conf_read(uint32_t cf8, uint8_t offset, uint8_t bytes); > void pci_conf_write(uint32_t cf8, uint8_t offset, uint8_t bytes, uint32_t data); > int pci_mmcfg_read(unsigned int seg, unsigned int bus, > -- > 2.20.1 (Apple Git-117) >
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 2e6529fba3..86273b6a07 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -707,11 +707,11 @@ static void init_amd(struct cpuinfo_x86 *c) (h & 0x1) ? "clearing D18F3x5C[0]" : ""); if (l & 0x1f) - pci_conf_write32(0, 0, 0x18, 3, 0x58, + pci_conf_write32(PCI_SBDF(0, 0, 0x18, 3), 0x58, l & ~0x1f); if (h & 0x1) - pci_conf_write32(0, 0, 0x18, 3, 0x5c, + pci_conf_write32(PCI_SBDF(0, 0, 0x18, 3), 0x5c, h & ~0x1); } diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index cbc1e3b3f0..9a1ce33b42 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -251,21 +251,17 @@ static int write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) { struct pci_dev *dev = entry->dev; int pos = entry->msi_attrib.pos; - u16 seg = dev->seg; - u8 bus = dev->bus; - u8 slot = PCI_SLOT(dev->devfn); - u8 func = PCI_FUNC(dev->devfn); int nr = entry->msi_attrib.entry_nr; ASSERT((msg->data & (entry[-nr].msi.nvec - 1)) == nr); if ( nr ) return 0; - pci_conf_write32(seg, bus, slot, func, msi_lower_address_reg(pos), + pci_conf_write32(dev->sbdf, msi_lower_address_reg(pos), msg->address_lo); if ( entry->msi_attrib.is_64 ) { - pci_conf_write32(seg, bus, slot, func, msi_upper_address_reg(pos), + pci_conf_write32(dev->sbdf, msi_upper_address_reg(pos), msg->address_hi); pci_conf_write16(dev->sbdf, msi_data_reg(pos, 1), msg->data); } @@ -395,7 +391,7 @@ static bool msi_set_mask_bit(struct irq_desc *desc, bool host, bool guest) mask_bits = pci_conf_read32(pdev->sbdf, entry->msi.mpos); mask_bits &= ~((u32)1 << entry->msi_attrib.entry_nr); mask_bits |= (u32)flag << entry->msi_attrib.entry_nr; - pci_conf_write32(seg, bus, slot, func, entry->msi.mpos, mask_bits); + pci_conf_write32(pdev->sbdf, entry->msi.mpos, mask_bits); } break; case PCI_CAP_ID_MSIX: @@ -716,7 +712,7 @@ static int msi_capability_init(struct pci_dev *dev, /* All MSIs are unmasked by default, Mask them all */ maskbits = pci_conf_read32(dev->sbdf, mpos); maskbits |= ~(u32)0 >> (32 - maxvec); - pci_conf_write32(seg, bus, slot, func, mpos, maskbits); + pci_conf_write32(dev->sbdf, mpos, maskbits); } list_add_tail(&entry->list, &dev->msi_list); diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofile/op_model_athlon.c index 3bf0b0214d..5c48f868ae 100644 --- a/xen/arch/x86/oprofile/op_model_athlon.c +++ b/xen/arch/x86/oprofile/op_model_athlon.c @@ -472,7 +472,9 @@ static int __init init_ibs_nmi(void) if ((vendor_id == PCI_VENDOR_ID_AMD) && (dev_id == PCI_DEVICE_ID_AMD_10H_NB_MISC)) { - pci_conf_write32(0, bus, dev, func, IBSCTL, + pci_conf_write32( + PCI_SBDF(0, bus, dev, func), + IBSCTL, IBSCTL_LVTOFFSETVAL | APIC_EILVT_LVTOFF_IBS); value = pci_conf_read32(PCI_SBDF(0, bus, dev, func), diff --git a/xen/arch/x86/x86_64/pci.c b/xen/arch/x86/x86_64/pci.c index f014fe0fc5..aad1c3f7cf 100644 --- a/xen/arch/x86/x86_64/pci.c +++ b/xen/arch/x86/x86_64/pci.c @@ -66,19 +66,10 @@ void pci_conf_write16(pci_sbdf_t sbdf, unsigned int reg, uint16_t data) pci_conf_write(PCI_CONF_ADDRESS(sbdf, reg), reg & 2, 2, data); } -#undef PCI_CONF_ADDRESS -#define PCI_CONF_ADDRESS(bus, dev, func, reg) \ - (0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3)) - -void pci_conf_write32( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, - unsigned int reg, uint32_t data) +void pci_conf_write32(pci_sbdf_t sbdf, unsigned int reg, uint32_t data) { - if ( seg || reg > 255 ) - pci_mmcfg_write(seg, bus, PCI_DEVFN(dev, func), reg, 4, data); + if ( sbdf.seg || reg > 255 ) + pci_mmcfg_write(sbdf.seg, sbdf.bus, sbdf.devfn, reg, 4, data); else - { - BUG_ON((bus > 255) || (dev > 31) || (func > 7)); - pci_conf_write(PCI_CONF_ADDRESS(bus, dev, func, reg), 0, 4, data); - } + pci_conf_write(PCI_CONF_ADDRESS(sbdf, reg), 0, 4, data); } diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c index b780334953..b6e155d17b 100644 --- a/xen/drivers/char/ehci-dbgp.c +++ b/xen/drivers/char/ehci-dbgp.c @@ -1012,7 +1012,8 @@ static void nvidia_set_debug_port(struct ehci_dbgp *dbgp, unsigned int port) dword &= ~(0x0f << 12); dword |= (port & 0x0f) << 12; - pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, 0x74, dword); + pci_conf_write32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), 0x74, + dword); dbgp_printk("set debug port to %u\n", port); } @@ -1436,7 +1437,7 @@ static void ehci_dbgp_resume(struct serial_port *port) if ( !dbgp->ehci_debug ) return; - pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, dbgp->bar, + pci_conf_write32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), dbgp->bar, dbgp->bar_val); pci_conf_write16(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), PCI_COMMAND, dbgp->pci_cr); diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 20eaecee59..e518f2d790 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -630,7 +630,8 @@ static void pci_serial_early_init(struct ns16550 *uart) (uart->io_base & 0xF000) | ((uart->io_base & 0xF000) >> 8)); - pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], + uart->ps_bdf[2]), PCI_BASE_ADDRESS_0, uart->io_base | PCI_BASE_ADDRESS_SPACE_IO); pci_conf_write16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], @@ -860,13 +861,14 @@ static void _ns16550_resume(struct serial_port *port) if ( uart->bar ) { - pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], + uart->ps_bdf[2]), PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->bar); /* If 64 bit BAR, write higher 32 bits to BAR+4 */ if ( uart->bar & PCI_BASE_ADDRESS_MEM_TYPE_64 ) - pci_conf_write32(0, uart->ps_bdf[0], - uart->ps_bdf[1], uart->ps_bdf[2], + pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], + uart->ps_bdf[2]), PCI_BASE_ADDRESS_0 + (uart->bar_idx+1)*4, uart->bar64); pci_conf_write16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1], @@ -1121,11 +1123,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) /* MMIO based */ if ( param->mmio && !(bar & PCI_BASE_ADDRESS_SPACE_IO) ) { - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); len = pci_conf_read32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx * 4); - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, bar); /* Handle 64 bit BAR if found */ @@ -1133,11 +1135,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) { bar_64 = pci_conf_read32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + (bar_idx + 1) * 4); - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ~0u); len_64 = pci_conf_read32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + (bar_idx + 1) * 4); - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, bar_64); size = ((u64)~0 << 32) | PCI_BASE_ADDRESS_MEM_MASK; size &= ((u64)len_64 << 32) | len; @@ -1151,11 +1153,11 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) /* IO based */ else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO) ) { - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); len = pci_conf_read32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0); - pci_conf_write32(0, b, d, f, + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, bar); size = len & PCI_BASE_ADDRESS_IO_MASK; diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthrough/amd/iommu_init.c index 6083d51b91..d19531493b 100644 --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -843,22 +843,22 @@ static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) (boot_cpu_data.x86_model > 0x1f) ) return; - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90); + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90); value = pci_conf_read32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf4); if ( value & (1 << 2) ) return; /* Select NB indirect register 0x90 and enable writing */ - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90 | (1 << 8)); + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90 | (1 << 8)); - pci_conf_write32(iommu->seg, bus, dev, func, 0xf4, value | (1 << 2)); + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf4, value | (1 << 2)); printk(XENLOG_INFO "AMD-Vi: Applying erratum 746 workaround for IOMMU at %04x:%02x:%02x.%u\n", iommu->seg, bus, dev, func); /* Clear the enable writing bit */ - pci_conf_write32(iommu->seg, bus, dev, func, 0xf0, 0x90); + pci_conf_write32(PCI_SBDF2(iommu->seg, iommu->bdf), 0xf0, 0x90); } static void enable_iommu(struct amd_iommu *iommu) diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index ff400e9a31..5271f8d69c 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -638,7 +638,7 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned int pos, ASSERT(!((flags & PCI_BAR_VF) && (flags & PCI_BAR_ROM))); ASSERT((flags & PCI_BAR_ROM) || (bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY); - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos, ~0); + pci_conf_write32(sbdf, pos, ~0); if ( is64bits ) { if ( flags & PCI_BAR_LAST ) @@ -651,17 +651,17 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned int pos, return 1; } hi = pci_conf_read32(sbdf, pos + 4); - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos + 4, ~0); + pci_conf_write32(sbdf, pos + 4, ~0); } size = pci_conf_read32(sbdf, pos) & mask; if ( is64bits ) { size |= (uint64_t)pci_conf_read32(sbdf, pos + 4) << 32; - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos + 4, hi); + pci_conf_write32(sbdf, pos + 4, hi); } else if ( size ) size |= (uint64_t)~0 << 32; - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, pos, bar); + pci_conf_write32(sbdf, pos, bar); size = -size; if ( paddr ) diff --git a/xen/drivers/passthrough/vtd/quirks.c b/xen/drivers/passthrough/vtd/quirks.c index 28e9597014..b6e2d313f0 100644 --- a/xen/drivers/passthrough/vtd/quirks.c +++ b/xen/drivers/passthrough/vtd/quirks.c @@ -441,7 +441,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) case 0x3728: /* Xeon C5500/C3500 (JasperForest) */ case 0x3c28: /* Sandybridge */ val = pci_conf_read32(pdev->sbdf, 0x1AC); - pci_conf_write32(seg, bus, dev, func, 0x1AC, val | (1 << 31)); + pci_conf_write32(pdev->sbdf, 0x1AC, val | (1 << 31)); printk(XENLOG_INFO "Masked VT-d error signaling on %04x:%02x:%02x.%u\n", seg, bus, dev, func); break; @@ -489,9 +489,9 @@ void pci_vtd_quirk(const struct pci_dev *pdev) action = "Found masked"; else if ( !ff ) { - pci_conf_write32(seg, bus, dev, func, pos + PCI_ERR_UNCOR_MASK, + pci_conf_write32(pdev->sbdf, pos + PCI_ERR_UNCOR_MASK, val | PCI_ERR_UNC_UNSUP); - pci_conf_write32(seg, bus, dev, func, pos + PCI_ERR_COR_MASK, + pci_conf_write32(pdev->sbdf, pos + PCI_ERR_COR_MASK, val2 | PCI_ERR_COR_ADV_NFAT); action = "Masked"; } @@ -500,7 +500,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) /* XPUNCERRMSK Send Completion with Unsupported Request */ val = pci_conf_read32(pdev->sbdf, 0x20c); - pci_conf_write32(seg, bus, dev, func, 0x20c, val | (1 << 4)); + pci_conf_write32(pdev->sbdf, 0x20c, val | (1 << 4)); printk(XENLOG_INFO "%s UR signaling on %04x:%02x:%02x.%u\n", action, seg, bus, dev, func); diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index f377e6abdf..3c794f486d 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -85,7 +85,6 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) { struct vpci_header *header = &pdev->vpci->header; - uint8_t slot = PCI_SLOT(pdev->devfn), func = PCI_FUNC(pdev->devfn); bool map = cmd & PCI_COMMAND_MEMORY; unsigned int i; @@ -113,7 +112,7 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, (map ? PCI_ROM_ADDRESS_ENABLE : 0); header->bars[i].enabled = header->rom_enabled = map; - pci_conf_write32(pdev->seg, pdev->bus, slot, func, rom_pos, val); + pci_conf_write32(pdev->sbdf, rom_pos, val); return; } @@ -395,7 +394,7 @@ static void bar_write(const struct pci_dev *pdev, unsigned int reg, val |= bar->prefetchable ? PCI_BASE_ADDRESS_MEM_PREFETCH : 0; } - pci_conf_write32(pdev->seg, pdev->bus, slot, func, reg, val); + pci_conf_write32(pdev->sbdf, reg, val); } static void rom_write(const struct pci_dev *pdev, unsigned int reg, @@ -426,7 +425,7 @@ static void rom_write(const struct pci_dev *pdev, unsigned int reg, { /* Just update the ROM BAR field. */ header->rom_enabled = new_enabled; - pci_conf_write32(pdev->seg, pdev->bus, slot, func, reg, val); + pci_conf_write32(pdev->sbdf, reg, val); } /* * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note that diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index b61672f295..ddbfa56489 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -253,7 +253,7 @@ static void vpci_write_hw(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, switch ( size ) { case 4: - pci_conf_write32(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, reg, data); + pci_conf_write32(sbdf, reg, data); break; case 3: diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index cb90d2f785..e6af45cfe7 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -177,9 +177,7 @@ uint16_t pci_conf_read16(pci_sbdf_t sbdf, unsigned int reg); uint32_t pci_conf_read32(pci_sbdf_t sbdf, unsigned int reg); void pci_conf_write8(pci_sbdf_t sbdf, unsigned int reg, uint8_t data); void pci_conf_write16(pci_sbdf_t sbdf, unsigned int reg, uint16_t data); -void pci_conf_write32( - unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func, - unsigned int reg, uint32_t data); +void pci_conf_write32(pci_sbdf_t sbdf, unsigned int reg, uint32_t data); uint32_t pci_conf_read(uint32_t cf8, uint8_t offset, uint8_t bytes); void pci_conf_write(uint32_t cf8, uint8_t offset, uint8_t bytes, uint32_t data); int pci_mmcfg_read(unsigned int seg, unsigned int bus,
This reduces the number of parameters of the function to two, and simplifies some of the calling sites. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> --- Cc: Jan Beulich <jbeulich@suse.com> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: Wei Liu <wl@xen.org> Cc: George Dunlap <George.Dunlap@eu.citrix.com> Cc: Ian Jackson <ian.jackson@eu.citrix.com> Cc: Julien Grall <julien.grall@arm.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Stefano Stabellini <sstabellini@kernel.org> Cc: Tim Deegan <tim@xen.org> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Brian Woods <brian.woods@amd.com> Cc: Kevin Tian <kevin.tian@intel.com> --- xen/arch/x86/cpu/amd.c | 4 ++-- xen/arch/x86/msi.c | 12 ++++-------- xen/arch/x86/oprofile/op_model_athlon.c | 4 +++- xen/arch/x86/x86_64/pci.c | 17 ++++------------- xen/drivers/char/ehci-dbgp.c | 5 +++-- xen/drivers/char/ns16550.c | 22 ++++++++++++---------- xen/drivers/passthrough/amd/iommu_init.c | 8 ++++---- xen/drivers/passthrough/pci.c | 8 ++++---- xen/drivers/passthrough/vtd/quirks.c | 8 ++++---- xen/drivers/vpci/header.c | 7 +++---- xen/drivers/vpci/vpci.c | 2 +- xen/include/xen/pci.h | 4 +--- 12 files changed, 45 insertions(+), 56 deletions(-)