From patchwork Mon Jun 10 19:32:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 10985367 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1F7B014BB for ; Mon, 10 Jun 2019 19:34:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0FA1527F17 for ; Mon, 10 Jun 2019 19:34:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 03C7D286CD; Mon, 10 Jun 2019 19:34:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9394D27F17 for ; Mon, 10 Jun 2019 19:34:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1haQ1w-0007h4-Hc; Mon, 10 Jun 2019 19:32:32 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1haQ1u-0007ez-SM for xen-devel@lists.xenproject.org; Mon, 10 Jun 2019 19:32:30 +0000 X-Inumbo-ID: 7ca62288-8bb6-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 7ca62288-8bb6-11e9-8980-bc764e045a96; Mon, 10 Jun 2019 19:32:30 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A096C0A; Mon, 10 Jun 2019 12:32:30 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 420733F73C; Mon, 10 Jun 2019 12:32:29 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 10 Jun 2019 20:32:07 +0100 Message-Id: <20190610193215.23704-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190610193215.23704-1-julien.grall@arm.com> References: <20190610193215.23704-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 09/17] xen/arm64: head: Improve coding style and document cpu_init() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , Stefano Stabellini , andrii_anisov@epam.com, Oleksandr_Tyshchenko@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Adjust the coding style used in the comments within cpu_init(). Take the opportunity to alter the early print to match the function name. Lastly, document the behavior and the main registers usage within the function. Signed-off-by: Julien Grall --- xen/arch/arm/arm64/head.S | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 6aa3148192..ee0024173e 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -396,19 +396,26 @@ skip_bss: ret ENDPROC(zero_bss) +/* + * Initialize the processor for turning the MMU on. + * + * Clobbers x0 - x4 + */ cpu_init: - PRINT("- Setting up control registers -\r\n") + PRINT("- Initialize CPU -\r\n") /* Set up memory attribute type tables */ ldr x0, =MAIRVAL msr mair_el2, x0 - /* Set up TCR_EL2: + /* + * Set up TCR_EL2: * PS -- Based on ID_AA64MMFR0_EL1.PARange * Top byte is used * PT walks use Inner-Shareable accesses, * PT walks are write-back, write-allocate in both cache levels, - * 48-bit virtual address space goes through this table. */ + * 48-bit virtual address space goes through this table. + */ ldr x0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(64-48)) /* ID_AA64MMFR0_EL1[3:0] (PARange) corresponds to TCR_EL2[18:16] (PS) */ mrs x1, ID_AA64MMFR0_EL1 @@ -427,9 +434,11 @@ cpu_init: ldr x0, =(HSCTLR_BASE) msr SCTLR_EL2, x0 - /* Ensure that any exceptions encountered at EL2 + /* + * Ensure that any exceptions encountered at EL2 * are handled using the EL2 stack pointer, rather - * than SP_EL0. */ + * than SP_EL0. + */ msr spsel, #1 ret ENDPROC(cpu_init)