From patchwork Wed Aug 7 00:23:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 11079727 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0328A912 for ; Wed, 7 Aug 2019 00:25:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E6A5B28837 for ; Wed, 7 Aug 2019 00:25:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DAF5F28849; Wed, 7 Aug 2019 00:25:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 57C1D28837 for ; Wed, 7 Aug 2019 00:25:05 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hv9jX-0004eR-Os; Wed, 07 Aug 2019 00:23:15 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hv9jX-0004dn-Ai for xen-devel@lists.xenproject.org; Wed, 07 Aug 2019 00:23:15 +0000 X-Inumbo-ID: 8b3e6983-b8a9-11e9-8980-bc764e045a96 Received: from mail.kernel.org (unknown [198.145.29.99]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 8b3e6983-b8a9-11e9-8980-bc764e045a96; Wed, 07 Aug 2019 00:23:13 +0000 (UTC) Received: from sstabellini-ThinkPad-T480s.xilinx.com (c-67-164-102-47.hsd1.ca.comcast.net [67.164.102.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 25CF5217D7; Wed, 7 Aug 2019 00:23:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1565137393; bh=xnN7N9SBAauUcp9S3b/w79ZpDs9tT93O9O8L4dJP124=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i6yo3+Nf52JavZbWcnKwa3hTrL8mOPNBpndy6+rNpYMbRXjQlqEpRa8WF92x8z2Iy 2zBMfwPHccd2zCbgDjGmpaEvuDxCXY6auyEB+s4zVkqN+kMZarYlz279hRO2sImIoP nJ1tJnksMN96Fc1J8HQVWRtWg0CoHGlqGqdY57PY= From: Stefano Stabellini To: xen-devel@lists.xenproject.org Date: Tue, 6 Aug 2019 17:23:08 -0700 Message-Id: <20190807002311.9906-3-sstabellini@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Subject: [Xen-devel] [PATCH v4 3/6] xen: extend XEN_DOMCTL_memory_mapping to handle memory policy X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , julien.grall@arm.com, sstabellini@kernel.org, JBeulich@suse.com, andrew.cooper3@citrix.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Reuse the existing padding field to pass memory policy information. On Arm, the caller can specify whether the memory should be mapped as Device-nGnRE (Device Memory on Armv7) at stage-2, which is the default and the only possibility today, or cacheable memory write-back. The resulting memory attributes will be a combination of stage-2 and stage-1 memory attributes: it will actually be the strongest between the 2 stages attributes. On x86, the only option is uncachable. The current behavior becomes the default (numerically '0'). Also explicitely set the memory_policy field to 0 in libxc. On Arm, map Device-nGnRE as p2m_mmio_direct_dev (as it is already done today) and WB cacheable memory as p2m_mmio_direct_c. On x86, there is just one policy which is the default. Signed-off-by: Stefano Stabellini CC: JBeulich@suse.com CC: andrew.cooper3@citrix.com --- Changes in v4: - return -EINVAL on XEN_DOMCTL_memory_mapping on default label - use MEMORY_POLICY_DEFAULT instead of 0 - uint32_t memory_policy -> unsigned int memory_policy - cache= -> policy= - MEMORY_POLICY_X86_UC_MINUS -> MEMORY_POLICY_DEFAULT - ARM -> Arm Changes in v3: - error handling in default label of the switch - set memory_policy to 0 in libxc - improve commit message - improve comments - s/Device-nGRE/Device-nGnRE/g - add in-code comment - s/MEMORY_POLICY_X86_UC/MEMORY_POLICY_X86_UC_MINUS/g - #ifdef hypercall defines according to arch Changes in v2: - rebase - use p2m_mmio_direct_c - use EOPNOTSUPP - rename cache_policy to memory policy - rename MEMORY_POLICY_DEVMEM to MEMORY_POLICY_ARM_DEV_nGRE - rename MEMORY_POLICY_MEMORY to MEMORY_POLICY_ARM_MEM_WB - add MEMORY_POLICY_X86_UC - add MEMORY_POLICY_DEFAULT and use it --- tools/libxc/xc_domain.c | 1 + xen/common/domctl.c | 25 +++++++++++++++++++++++-- xen/include/public/domctl.h | 20 +++++++++++++++++++- 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/tools/libxc/xc_domain.c b/tools/libxc/xc_domain.c index 05d771f2ce..075ffb9ed1 100644 --- a/tools/libxc/xc_domain.c +++ b/tools/libxc/xc_domain.c @@ -2070,6 +2070,7 @@ int xc_domain_memory_mapping( domctl.cmd = XEN_DOMCTL_memory_mapping; domctl.domain = domid; domctl.u.memory_mapping.add_mapping = add_mapping; + domctl.u.memory_mapping.memory_policy = MEMORY_POLICY_DEFAULT; max_batch_sz = nr_mfns; do { diff --git a/xen/common/domctl.c b/xen/common/domctl.c index 2674caa005..063523c7f7 100644 --- a/xen/common/domctl.c +++ b/xen/common/domctl.c @@ -920,6 +920,7 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) unsigned long mfn_end = mfn + nr_mfns - 1; int add = op->u.memory_mapping.add_mapping; p2m_type_t p2mt; + unsigned int memory_policy = op->u.memory_mapping.memory_policy; ret = -EINVAL; if ( mfn_end < mfn || /* wrap? */ @@ -950,9 +951,29 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) if ( add ) { printk(XENLOG_G_DEBUG - "memory_map:add: dom%d gfn=%lx mfn=%lx nr=%lx\n", - d->domain_id, gfn, mfn, nr_mfns); + "memory_map:add: dom%d gfn=%lx mfn=%lx nr=%lx policy=%u\n", + d->domain_id, gfn, mfn, nr_mfns, memory_policy); + switch ( memory_policy ) + { +#ifdef CONFIG_ARM + case MEMORY_POLICY_ARM_MEM_WB: + p2mt = p2m_mmio_direct_c; + break; + case MEMORY_POLICY_ARM_DEV_nGnRE: + p2mt = p2m_mmio_direct_dev; + break; +#endif +#ifdef CONFIG_X86 + case MEMORY_POLICY_DEFAULT: + p2mt = p2m_mmio_direct; + break; +#endif + default: + domctl_lock_release(); + ret = -EINVAL; + goto domctl_out_unlock_domonly; + } ret = map_mmio_regions(d, _gfn(gfn), nr_mfns, _mfn(mfn), p2mt); if ( ret < 0 ) printk(XENLOG_G_WARNING diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 19486d5e32..b9078400fa 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -571,12 +571,30 @@ struct xen_domctl_bind_pt_irq { */ #define DPCI_ADD_MAPPING 1 #define DPCI_REMOVE_MAPPING 0 +/* + * Default memory policy. Corresponds to: + * Arm: MEMORY_POLICY_ARM_DEV_nGnRE + * x86: Memory type UNCACHABLE + */ +#define MEMORY_POLICY_DEFAULT 0 +#if defined(__arm__) || defined (__aarch64__) +/* Arm only. Outer Shareable, Device-nGnRE memory (Device Memory on Armv7) */ +# define MEMORY_POLICY_ARM_DEV_nGnRE 0 +/* Arm only. Outer Shareable, Outer/Inner Write-Back Cacheable memory */ +# define MEMORY_POLICY_ARM_MEM_WB 1 +/* + * On Arm, MEMORY_POLICY selects the stage-2 memory attributes, but note + * that the resulting memory attributes will be a combination of stage-2 + * and stage-1 memory attributes: it will be the strongest between the 2 + * stages attributes. + */ +#endif struct xen_domctl_memory_mapping { uint64_aligned_t first_gfn; /* first page (hvm guest phys page) in range */ uint64_aligned_t first_mfn; /* first page (machine page) in range */ uint64_aligned_t nr_mfns; /* number of pages in range (>0) */ uint32_t add_mapping; /* add or remove mapping */ - uint32_t padding; /* padding for 64-bit aligned structure */ + uint32_t memory_policy; /* cacheability of the memory mapping */ };