[v3,16/28] xen/arm32: head: Document create_pages_tables()

Message ID	20190812173019.11956-17-julien.grall@arm.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <xen-devel-bounces@lists.xenproject.org> From: Julien Grall <julien.grall@arm.com> To: xen-devel@lists.xenproject.org Date: Mon, 12 Aug 2019 18:30:07 +0100 Message-Id: <20190812173019.11956-17-julien.grall@arm.com> In-Reply-To: <20190812173019.11956-1-julien.grall@arm.com> References: <20190812173019.11956-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v3 16/28] xen/arm32: head: Document create_pages_tables() Precedence: list Cc: Julien Grall <julien.grall@arm.com>, Stefano Stabellini <sstabellini@kernel.org>, Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" <xen-devel-bounces@lists.xenproject.org>
Series	xen/arm: Rework head.S to make it more compliant with the Arm Arm \| expand [v3,00/28] xen/arm: Rework head.S to make it more compliant with the Arm Arm [v3,01/28] xen/arm: lpae: Allow more LPAE helpers to be used in assembly [v3,02/28] xen/arm64: head: Remove 1:1 mapping as soon as it is not used [v3,03/28] xen/arm64: head: Rework and document setup_fixmap() [v3,04/28] xen/arm64: head: Rework and document launch() [v3,05/28] xen/arm64: head: Setup TTBR_EL2 in enable_mmu() and add missing isb [v3,06/28] xen/arm64: head: Introduce a macro to get a PC-relative address of a symbol [v3,07/28] xen/arm64: head: Fix typo in the documentation on top of init_uart() [v3,08/28] xen/arm32: head: Add a macro to move an immediate constant into a 32-bit register [v3,09/28] xen/arm32: head: Mark the end of subroutines with ENDPROC [v3,10/28] xen/arm32: head: Don't clobber r14/lr in the macro PRINT [v3,11/28] xen/arm32: head: Rework UART initialization on boot CPU [v3,12/28] xen/arm32: head: Introduce print_reg [v3,13/28] xen/arm32: head: Introduce distinct paths for the boot CPU and secondary CPUs [v3,14/28] xen/arm32: head: Rework and document check_cpu_mode() [v3,15/28] xen/arm32: head: Rework and document zero_bss() [v3,16/28] xen/arm32: head: Document create_pages_tables() [v3,17/28] xen/arm32: head: Document enable_mmu() [v3,18/28] xen/arm32: head: Move assembly switch to the runtime PT in secondary CPUs path [v3,19/28] xen/arm32: head: Don't setup the fixmap on secondary CPUs [v3,20/28] xen/arm32: head: Remove 1:1 mapping as soon as it is not used [v3,21/28] xen/arm32: head: Rework and document setup_fixmap() [v3,22/28] xen/arm32: head: Rework and document launch() [v3,23/28] xen/arm32: head: Setup HTTBR in enable_mmu() and add missing isb [v3,24/28] xen/arm: Zero BSS after the MMU and D-cache is turned on [v3,25/28] xen/arm64: head: Introduce macros to create table and mapping entry [v3,26/28] xen/arm64: head: Use a page mapping for the 1:1 mapping in create_page_tables() [v3,27/28] xen/arm32: head: Introduce macros to create table and mapping entry [v3,28/28] xen/arm32: head: Use a page mapping for the 1:1 mapping in create_page_tables()

Message ID

20190812173019.11956-17-julien.grall@arm.com (mailing list archive)

State

Superseded

Headers

From: Julien Grall <julien.grall@arm.com>
To: xen-devel@lists.xenproject.org
Date: Mon, 12 Aug 2019 18:30:07 +0100
Message-Id: <20190812173019.11956-17-julien.grall@arm.com>
In-Reply-To: <20190812173019.11956-1-julien.grall@arm.com>
References: <20190812173019.11956-1-julien.grall@arm.com>
Subject: [Xen-devel] [PATCH v3 16/28] xen/arm32: head: Document
 create_pages_tables()
Precedence: list
Cc: Julien Grall <julien.grall@arm.com>,
 Stefano Stabellini <sstabellini@kernel.org>,
 Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: xen-devel-bounces@lists.xenproject.org
Sender: "Xen-devel" <xen-devel-bounces@lists.xenproject.org>

Series

xen/arm: Rework head.S to make it more compliant with the Arm Arm | expand

Commit Message

Julien Grall Aug. 12, 2019, 5:30 p.m. UTC

Document the behavior and the main registers usage within the function.
Note that r6 is now only used within the function, so it does not need
to be part of the common register.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>

---
    Changes in v3:
        - Add Stefano's acked-by

    Changes in v2:
        - Patch added
---
 xen/arch/arm/arm32/head.S | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 1189ed6c47..83f8774e2a 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -53,7 +53,7 @@ 
  *   r3  -
  *   r4  -
  *   r5  -
- *   r6  - identity map in place
+ *   r6  -
  *   r7  -
  *   r8  - DTB address (boot CPU only)
  *   r9  - paddr(start)
@@ -302,18 +302,26 @@  cpu_init_done:
         mov   pc, r5                        /* Return address is in r5 */
 ENDPROC(cpu_init)
 
+/*
+ * Rebuild the boot pagetable's first-level entries. The structure
+ * is described in mm.c.
+ *
+ * After the CPU enables paging it will add the fixmap mapping
+ * to these page tables, however this may clash with the 1:1
+ * mapping. So each CPU must rebuild the page tables here with
+ * the 1:1 in place.
+ *
+ * Inputs:
+ *   r9 : paddr(start)
+ *   r10: phys offset
+ *
+ * Clobbers r0 - r6
+ *
+ * Register usage within this function:
+ *   r6 : Identity map in place
+ */
 create_page_tables:
         /*
-         * Rebuild the boot pagetable's first-level entries. The structure
-         * is described in mm.c.
-         *
-         * After the CPU enables paging it will add the fixmap mapping
-         * to these page tables, however this may clash with the 1:1
-         * mapping. So each CPU must rebuild the page tables here with
-         * the 1:1 in place.
-         */
-
-        /*
          * If Xen is loaded at exactly XEN_VIRT_START then we don't
          * need an additional 1:1 mapping, the virtual mapping will
          * suffice.