From patchwork Tue Sep 24 14:35:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 11159005 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0012E14ED for ; Tue, 24 Sep 2019 14:36:47 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5C3E2053B for ; Tue, 24 Sep 2019 14:36:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5C3E2053B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iCluX-0000QG-EM; Tue, 24 Sep 2019 14:35:25 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iCluW-0000Q9-3j for xen-devel@lists.xenproject.org; Tue, 24 Sep 2019 14:35:24 +0000 X-Inumbo-ID: 89c5708e-ded8-11e9-bf31-bc764e2007e4 Received: from foss.arm.com (unknown [217.140.110.172]) by localhost (Halon) with ESMTP id 89c5708e-ded8-11e9-bf31-bc764e2007e4; Tue, 24 Sep 2019 14:35:21 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5D5D31570; Tue, 24 Sep 2019 07:35:21 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AC1D53F59C; Tue, 24 Sep 2019 07:35:20 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 24 Sep 2019 15:35:14 +0100 Message-Id: <20190924143515.8810-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190924143515.8810-1-julien.grall@arm.com> References: <20190924143515.8810-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.13 v2 1/2] xen/arm: Implement workaround for Cortex A-57 and Cortex A72 AT speculate X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Both Cortex-A57 (erratum 1319537) and Cortex-A72 (erratum 1319367) can end with corrupt TLBs if they speculate an AT instruction while S1/S2 system registers in inconsistent state. The workaround is the same as for Cortex A-76 implemented by commit a18be06aca "xen/arm: Implement workaround for Cortex-A76 erratum 1165522", so it is only necessary to plumb in the cpuerrata framework. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Add missing | --- docs/misc/arm/silicon-errata.txt | 2 ++ xen/arch/arm/cpuerrata.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index 6cd1366f15..11e5a9dcec 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt @@ -48,5 +48,7 @@ stable hypervisors. | ARM | Cortex-A57 | #852523 | N/A | | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +| ARM | Cortex-A57 | #1319537 | N/A | +| ARM | Cortex-A72 | #1319367 | N/A | | ARM | Cortex-A76 | #1165522 | N/A | | ARM | MMU-500 | #842869 | N/A | diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 6f483b2d8d..da72b02442 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -481,6 +481,16 @@ static const struct arm_cpu_capabilities arm_errata[] = { .capability = ARM64_WORKAROUND_AT_SPECULATE, MIDR_RANGE(MIDR_CORTEX_A76, 0, 2 << MIDR_VARIANT_SHIFT), }, + { + .desc = "ARM erratum 1319537", + .capability = ARM64_WORKAROUND_AT_SPECULATE, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + }, + { + .desc = "ARM erratum 1319367", + .capability = ARM64_WORKAROUND_AT_SPECULATE, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + }, {}, };