From patchwork Fri Nov 22 02:24:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11257185 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3108414C0 for ; Fri, 22 Nov 2019 05:18:39 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D3942068E for ; Fri, 22 Nov 2019 05:18:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="NCJD76gl" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D3942068E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iY1Jv-0006EG-1f; Fri, 22 Nov 2019 05:17:27 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iXycN-0001Gi-E6 for xen-devel@lists.xenproject.org; Fri, 22 Nov 2019 02:24:19 +0000 X-Inumbo-ID: 2bbadca2-0ccf-11ea-adbe-bc764e2007e4 Received: from mail-qt1-x844.google.com (unknown [2607:f8b0:4864:20::844]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 2bbadca2-0ccf-11ea-adbe-bc764e2007e4; Fri, 22 Nov 2019 02:24:12 +0000 (UTC) Received: by mail-qt1-x844.google.com with SMTP id o49so6122874qta.7 for ; Thu, 21 Nov 2019 18:24:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HgQtjc5acLHzjiwVf/zPdL0W3rJRgxp/Mq6B1WIDDxY=; b=NCJD76glok7tVpPWeRPMFMOTsJyN4W7x2c/GCYOWTwrHjqgkhGGyM4V97AkUHi7MJ8 KGTYQXByuaFA/HeJ/VPbTjcCKJ1GKPTm/770K7AeT6xPogT8ulU3rOP9qd11J7e3lcP1 QpEXRRxNPL/pyJn7e5Km8+UTwxnuBqX2xB6z45Aodil6sdu5WtiHlqtHjexiVH9xBs9h zn9vt/ZcjNmX4zQzavX5aYNETygv+Fy21dmaPT6M8AV/hr7nhpf+0pCuDj86VttXSygY B+SFKXJNsZUDaDYm066fXl8fGA4gF2/m3CEO9ntre4m2w/kNPPa7QP6LMBMl3WSEEyFs xtLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HgQtjc5acLHzjiwVf/zPdL0W3rJRgxp/Mq6B1WIDDxY=; b=Ht9NUfV5ovYYvbPFV6EQzX9xFS5vJVifxUGTzUlvufD1l9UYTZx+hXb3kKGQ6CLEq9 fYgfhvmTnBwppX7NCy2rurUqrjynnQz4YFU5QEOCi821RaVti+Bkan2zjtXWYL3niPux +RuVdDMMSz8vZVDG6ZuZ1/ZwDzsYeqI5SbSM1YaWoFYGZg0EVbkEFcFfdjO9qufbWP29 CjtqAPAMP0tAsbGudwxvv04nNzwBRu1Xk1kCsA8AC0a0Bo1awizHg0Rlm5Puldn8VOEy B/EbckJ1HxKWHGp1OMZejgfvhCsVI+7+pJicW/Q1sjn0ocBDzQjnfKRa5xuDbLrmnf7Z 4Igg== X-Gm-Message-State: APjAAAWEza+bo781Qs9tzknulB9Zhl/U/fwZc6O2idqWdW24ohuKTNTZ To5gFZpMKwshLn23/TNPHwjLbw== X-Google-Smtp-Source: APXvYqyII7bwvpdPFvB1uClYqq9YlCH8qAJI5DdRg1eAxlpjXNOJ/Xqjeo/s4oaH3hLXKnjnqntnXg== X-Received: by 2002:ac8:1084:: with SMTP id a4mr12202956qtj.114.1574389451666; Thu, 21 Nov 2019 18:24:11 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id z5sm2609801qtm.9.2019.11.21.18.24.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 18:24:11 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk Date: Thu, 21 Nov 2019 21:24:05 -0500 Message-Id: <20191122022406.590141-3-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191122022406.590141-1-pasha.tatashin@soleen.com> References: <20191122022406.590141-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 22 Nov 2019 05:17:22 +0000 Subject: [Xen-devel] [PATCH v2 2/3] arm64: remove uaccess_ttbr0 asm macros from cache functions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Replace the uaccess_ttbr0_disable/uaccess_ttbr0_enable via inline variants, and remove asm macros. Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/asm-uaccess.h | 22 ---------------- arch/arm64/include/asm/cacheflush.h | 38 +++++++++++++++++++++++++--- arch/arm64/mm/cache.S | 30 ++++++++-------------- arch/arm64/mm/flush.c | 2 +- 4 files changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h index 35e6145e1402..8f763e5b41b1 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -34,27 +34,5 @@ msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 isb .endm - - .macro uaccess_ttbr0_disable, tmp1, tmp2 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp2 // avoid preemption - __uaccess_ttbr0_disable \tmp1 - restore_irq \tmp2 -alternative_else_nop_endif - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp3 // avoid preemption - __uaccess_ttbr0_enable \tmp1, \tmp2 - restore_irq \tmp3 -alternative_else_nop_endif - .endm -#else - .macro uaccess_ttbr0_disable, tmp1, tmp2 - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 - .endm #endif #endif diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 665c78e0665a..cdd4a8eb8708 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -61,16 +61,48 @@ * - kaddr - page address * - size - region size */ -extern void __flush_icache_range(unsigned long start, unsigned long end); -extern int invalidate_icache_range(unsigned long start, unsigned long end); +extern void __arch_flush_icache_range(unsigned long start, unsigned long end); +extern long __arch_flush_cache_user_range(unsigned long start, + unsigned long end); +extern int arch_invalidate_icache_range(unsigned long start, + unsigned long end); + extern void __flush_dcache_area(void *addr, size_t len); extern void __inval_dcache_area(void *addr, size_t len); extern void __clean_dcache_area_poc(void *addr, size_t len); extern void __clean_dcache_area_pop(void *addr, size_t len); extern void __clean_dcache_area_pou(void *addr, size_t len); -extern long __flush_cache_user_range(unsigned long start, unsigned long end); extern void sync_icache_aliases(void *kaddr, unsigned long len); +static inline void __flush_icache_range(unsigned long start, unsigned long end) +{ + uaccess_ttbr0_enable(); + __arch_flush_icache_range(start, end); + uaccess_ttbr0_disable(); +} + +static inline void __flush_cache_user_range(unsigned long start, + unsigned long end) +{ + uaccess_ttbr0_enable(); + __arch_flush_cache_user_range(start, end); + uaccess_ttbr0_disable(); +} + +static inline int invalidate_icache_range(unsigned long start, + unsigned long end) +{ + int rv; +#if ARM64_HAS_CACHE_DIC + rv = arch_invalidate_icache_range(start, end); +#else + uaccess_ttbr0_enable(); + rv = arch_invalidate_icache_range(start, end); + uaccess_ttbr0_disable(); +#endif + return rv; +} + static inline void flush_icache_range(unsigned long start, unsigned long end) { __flush_icache_range(start, end); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index db767b072601..408d317a47d2 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -15,7 +15,7 @@ #include /* - * flush_icache_range(start,end) + * __arch_flush_icache_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, @@ -24,11 +24,11 @@ * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(__flush_icache_range) +ENTRY(__arch_flush_icache_range) /* FALLTHROUGH */ /* - * __flush_cache_user_range(start,end) + * __arch_flush_cache_user_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, @@ -37,8 +37,7 @@ ENTRY(__flush_icache_range) * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(__flush_cache_user_range) - uaccess_ttbr0_enable x2, x3, x4 +ENTRY(__arch_flush_cache_user_range) alternative_if ARM64_HAS_CACHE_IDC dsb ishst b 7f @@ -60,14 +59,11 @@ alternative_if ARM64_HAS_CACHE_DIC alternative_else_nop_endif invalidate_icache_by_line x0, x1, x2, x3, 9f 8: mov x0, #0 -1: - uaccess_ttbr0_disable x1, x2 - ret -9: - mov x0, #-EFAULT +1: ret +9: mov x0, #-EFAULT b 1b -ENDPROC(__flush_icache_range) -ENDPROC(__flush_cache_user_range) +ENDPROC(__arch_flush_icache_range) +ENDPROC(__arch_flush_cache_user_range) /* * invalidate_icache_range(start,end) @@ -83,16 +79,10 @@ alternative_if ARM64_HAS_CACHE_DIC isb ret alternative_else_nop_endif - - uaccess_ttbr0_enable x2, x3, x4 - invalidate_icache_by_line x0, x1, x2, x3, 2f mov x0, xzr -1: - uaccess_ttbr0_disable x1, x2 - ret -2: - mov x0, #-EFAULT +1: ret +2: mov x0, #-EFAULT b 1b ENDPROC(invalidate_icache_range) diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index ac485163a4a7..66249fca2092 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -75,7 +75,7 @@ EXPORT_SYMBOL(flush_dcache_page); /* * Additional functions defined in assembly. */ -EXPORT_SYMBOL(__flush_icache_range); +EXPORT_SYMBOL(__arch_flush_icache_range); #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size)