From patchwork Wed Dec 4 15:12:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 11273067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF921109A for ; Wed, 4 Dec 2019 15:14:23 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B133A2081B for ; Wed, 4 Dec 2019 15:14:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="HloNe0DG" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B133A2081B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=citrix.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icWKt-0007vD-6o; Wed, 04 Dec 2019 15:13:03 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icWKs-0007v8-3z for xen-devel@lists.xenproject.org; Wed, 04 Dec 2019 15:13:02 +0000 X-Inumbo-ID: 8f6ca91e-16a8-11ea-9c09-bc764e2007e4 Received: from esa2.hc3370-68.iphmx.com (unknown [216.71.145.153]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 8f6ca91e-16a8-11ea-9c09-bc764e2007e4; Wed, 04 Dec 2019 15:13:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1575472381; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=LYlNAdMhxQZ1m+Ojk/FGSXu17tdP+HmX5ldv9W2jdd4=; b=HloNe0DGaS2jdmqoK5jZQRy26fqo/3eT7UEraQw5H8IwU8RvDoJoBecl R59ny3zemXFrSqSdyc2dPLF6SqDTttnLR7VNkKi52jz6FFwuHpJG4tAXP Vwyu0bpdF3h28IGuIqhi28Ng6YZtaIcxfdNHHusqHsz1hFHGNZJEUbjKt E=; Authentication-Results: esa2.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=roger.pau@citrix.com; spf=Pass smtp.mailfrom=roger.pau@citrix.com; spf=None smtp.helo=postmaster@mail.citrix.com Received-SPF: None (esa2.hc3370-68.iphmx.com: no sender authenticity information available from domain of roger.pau@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa2.hc3370-68.iphmx.com: domain of roger.pau@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ip4:168.245.78.127 ~all" Received-SPF: None (esa2.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: 2PIfGPZufqSVYPQ+uy0KxtJcCeB1b2mF83VbyWKPd7fPXxhZD7A0NuXn8dyOmEXaOmcRon9Itb V8NbcmTTiBkGpQqS7B4RIKcjMdefAPTlnkB/koyXW/xk5uC3qa967cQmoqhKHbADy1Tq91EzVg nHb7lOtQ741LRyqvX3bl6wFR7YBBPfuq78e3A+kkkxTMoehZJqKMqXdL27cgzfdLmAc2R9WAbY 6oaYe0bqR6GOT39PLWl90jT9D7K/+mpYPUqrtMKyp5Q4oHUv7Dzs40F7rfBveZ8Q1lN5DnDTWQ kFE= X-SBRS: 2.7 X-MesageID: 9195584 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,277,1571716800"; d="scan'208";a="9195584" From: Roger Pau Monne To: Date: Wed, 4 Dec 2019 16:12:08 +0100 Message-ID: <20191204151208.37076-1-roger.pau@citrix.com> X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v3] x86: do not enable global pages when virtualized on AMD hardware X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Julien Grall , Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Andrew Cooper , Ian Jackson , Jan Beulich , Roger Pau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When using global pages a full tlb flush can only be performed by toggling the PGE bit in CR4, which is usually quite expensive in terms of performance when running virtualized. This is specially relevant on AMD hardware, which doesn't have the ability to do selective CR4 trapping, but can also be relevant on Intel if the underlying hypervisor also traps accesses to the PGE CR4 bit. In order to avoid this performance penalty, do not use global pages when running virtualized on AMD hardware. A command line option 'global-pages' is provided in order to allow the user to select whether global pages will be enabled for PV guests. The above figures are from a PV shim running on AMD hardware with 32 vCPUs: PGE enabled, x2APIC mode: (XEN) Global lock flush_lock: addr=ffff82d0804b01c0, lockval=1adb1adb, not locked (XEN) lock:1841883(1375128998543), block:1658716(10193054890781) Average lock time: 746588ns Average block time: 6145147ns PGE disabled, x2APIC mode: (XEN) Global lock flush_lock: addr=ffff82d0804af1c0, lockval=a8bfa8bf, not locked (XEN) lock:2730175(657505389886), block:2039716(2963768247738) Average lock time: 240829ns Average block time: 1453029ns As seen from the above figures the lock and block time of the flush lock is reduced to approximately 1/3 of the original value. Signed-off-by: Roger Pau Monné --- Changes since v2: - Set the default value at init if not specified by the user. - Use int8_t and read_mostly for opt_global_pages. Changes since v1: - Provide command line option to enable/disable PGE. - Only disable PGE on AMD hardware when virtualized. - Document the global-pages option. --- docs/misc/xen-command-line.pandoc | 13 +++++++++++++ xen/arch/x86/pv/domain.c | 15 ++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index d9495ef6b9..7be30f2766 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1087,6 +1087,19 @@ value settable via Xen tools. Dom0 is using this value for sizing its maptrack table. +### global-pages (x86) +> `= ` + +> Default: `true` unless running virtualized on AMD hardware + +Set whether the PGE bit in CR4 will be enabled for PV guests. This controls the +usage of global pages, and thus the need to perform tlb flushes by writing to +CR4. + +Note it's disabled by default when running virtualized on AMD hardware since +AMD SVM doesn't support selective trapping of CR4, so global pages are not +enabled in order to reduce the overhead of tlb flushes. + ### guest_loglvl > `= [/]` where level is `none | error | warning | info | debug | all` diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index 4b6f48dea2..8ff733f56b 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -118,6 +118,19 @@ unsigned long pv_fixup_guest_cr4(const struct vcpu *v, unsigned long cr4) (mmu_cr4_features & PV_CR4_GUEST_VISIBLE_MASK)); } +static int8_t __read_mostly opt_global_pages = -1; +boolean_runtime_param("global-pages", opt_global_pages); + +static int __init pge_init(void) +{ + if ( opt_global_pages == -1 ) + opt_global_pages = !cpu_has_hypervisor || + boot_cpu_data.x86_vendor != X86_VENDOR_AMD; + + return 0; +} +__initcall(pge_init); + unsigned long pv_make_cr4(const struct vcpu *v) { const struct domain *d = v->domain; @@ -130,7 +143,7 @@ unsigned long pv_make_cr4(const struct vcpu *v) */ if ( d->arch.pv.pcid ) cr4 |= X86_CR4_PCIDE; - else if ( !d->arch.pv.xpti ) + else if ( !d->arch.pv.xpti && opt_global_pages ) cr4 |= X86_CR4_PGE; /*