From patchwork Mon Dec 23 16:43:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Dunlap X-Patchwork-Id: 11308521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 41C89109A for ; Mon, 23 Dec 2019 16:46:11 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1E2452073A for ; Mon, 23 Dec 2019 16:46:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="KwLHx/uJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1E2452073A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=citrix.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1ijQoA-0006Kn-Kd; Mon, 23 Dec 2019 16:43:50 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1ijQo8-0006KG-V5 for xen-devel@lists.xenproject.org; Mon, 23 Dec 2019 16:43:48 +0000 X-Inumbo-ID: 5c36a6da-25a3-11ea-96fe-12813bfff9fa Received: from esa1.hc3370-68.iphmx.com (unknown [216.71.145.142]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 5c36a6da-25a3-11ea-96fe-12813bfff9fa; Mon, 23 Dec 2019 16:43:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1577119414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vsbhqvxTPqxq150MwF1GoyaiUXnxXCxdKv0AX0i+w4A=; b=KwLHx/uJU2tWJiLH6hKiz+Bk10NTE1NbIwHv0OjtSqwLMlKinKcHckWq /Tl0KWaPupeTJygqSvH2nWD8lmGHj3WTko3MpYXsCuToXTzYu7wnIp5jb r/PE3QBq3Ek0jAUyPhN7m3gM6y4LFnvpSR6Hhh5ZKQnFkMIthiZII2rDj s=; Authentication-Results: esa1.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=george.dunlap@citrix.com; spf=Pass smtp.mailfrom=George.Dunlap@citrix.com; spf=None smtp.helo=postmaster@mail.citrix.com Received-SPF: None (esa1.hc3370-68.iphmx.com: no sender authenticity information available from domain of george.dunlap@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa1.hc3370-68.iphmx.com; envelope-from="George.Dunlap@citrix.com"; x-sender="george.dunlap@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa1.hc3370-68.iphmx.com: domain of George.Dunlap@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa1.hc3370-68.iphmx.com; envelope-from="George.Dunlap@citrix.com"; x-sender="George.Dunlap@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ip4:168.245.78.127 ~all" Received-SPF: None (esa1.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa1.hc3370-68.iphmx.com; envelope-from="George.Dunlap@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: 7yCzjNOIXE9cMcr2KHNYPhVUxnpjVBL9i5LUbLITtj9830IRWyE98T/XwFbO7hF793u7hLd/tS q8p+dsEsxrvEFZ/4obU8sk3o29Uhrk3svBGG2iIixBy5nMCAr8jO//ZaXHLtzSa8g2dVFLGq7Q R87ogzktdYXJ20D9IIoiBylAWOL37ekWC0TnFAk8yFGULHoyotomVSFNhHeAD29CWZPNtwO0uG TU6ES15VDEM4Yys1DFw5vWSgqjQEh0YXtvigmkZ2pOHLdCmphj80Q9y1FYVY1tqUhUgZHF2o/F FVg= X-SBRS: 2.7 X-MesageID: 10229662 X-Ironport-Server: esa1.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,348,1571716800"; d="scan'208";a="10229662" From: George Dunlap To: Date: Mon, 23 Dec 2019 16:43:26 +0000 Message-ID: <20191223164329.3113378-2-george.dunlap@citrix.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191223164329.3113378-1-george.dunlap@citrix.com> References: <20191223164329.3113378-1-george.dunlap@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 1/4] xen: Remove trailing whitespace from time.c X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , George Dunlap , Jan Beulich Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" No functional changes. Signed-off-by: George Dunlap Acked-by: Jan Beulich --- CC: Andrew Cooper CC: Jan Beulich --- xen/arch/x86/time.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index ea696a95e8..64e471a39b 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -1,10 +1,10 @@ /****************************************************************************** * arch/x86/time.c - * + * * Per-CPU time calibration and management. - * + * * Copyright (c) 2002-2005, K A Fraser - * + * * Portions from Linux are: * Copyright (c) 1991, 1992, 1995 Linus Torvalds */ @@ -78,8 +78,8 @@ static struct timer calibration_timer; * We simulate a 32-bit platform timer from the 16-bit PIT ch2 counter. * Otherwise overflow happens too quickly (~50ms) for us to guarantee that * softirq handling will happen in time. - * - * The pit_lock protects the 16- and 32-bit stamp fields as well as the + * + * The pit_lock protects the 16- and 32-bit stamp fields as well as the */ static DEFINE_SPINLOCK(pit_lock); static u16 pit_stamp16; @@ -100,7 +100,7 @@ static inline u32 div_frac(u32 dividend, u32 divisor) { u32 quotient, remainder; ASSERT(dividend < divisor); - asm ( + asm ( "divl %4" : "=a" (quotient), "=d" (remainder) : "0" (0), "1" (dividend), "r" (divisor) ); @@ -1011,7 +1011,7 @@ static void __get_cmos_time(struct rtc_time *rtc) rtc->day = CMOS_READ(RTC_DAY_OF_MONTH); rtc->mon = CMOS_READ(RTC_MONTH); rtc->year = CMOS_READ(RTC_YEAR); - + if ( RTC_ALWAYS_BCD || !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) ) { BCD_TO_BIN(rtc->sec); @@ -1511,8 +1511,8 @@ static void check_tsc_warp(unsigned long tsc_khz, unsigned long *max_warp) spin_unlock(&sync_lock); /* - * Be nice every now and then (and also check whether measurement is - * done [we also insert a 10 million loops safety exit, so we dont + * Be nice every now and then (and also check whether measurement is + * done [we also insert a 10 million loops safety exit, so we dont * lock up in case the TSC readout is totally broken]): */ if ( unlikely(!(i & 7)) ) @@ -1524,7 +1524,7 @@ static void check_tsc_warp(unsigned long tsc_khz, unsigned long *max_warp) } /* - * Outside the critical section we can now see whether we saw a + * Outside the critical section we can now see whether we saw a * time-warp of the TSC going backwards: */ if ( unlikely(prev > now) ) @@ -1806,11 +1806,11 @@ void init_percpu_time(void) } /* - * On certain older Intel CPUs writing the TSC MSR clears the upper 32 bits. + * On certain older Intel CPUs writing the TSC MSR clears the upper 32 bits. * Obviously we must not use write_tsc() on such CPUs. * - * Additionally, AMD specifies that being able to write the TSC MSR is not an - * architectural feature (but, other than their manual says, also cannot be + * Additionally, AMD specifies that being able to write the TSC MSR is not an + * architectural feature (but, other than their manual says, also cannot be * determined from CPUID bits). */ static void __init tsc_check_writability(void) @@ -2010,7 +2010,7 @@ void __init early_time_init(void) do_div(tmp, 1000); cpu_khz = (unsigned long)tmp; - printk("Detected %lu.%03lu MHz processor.\n", + printk("Detected %lu.%03lu MHz processor.\n", cpu_khz / 1000, cpu_khz % 1000); setup_irq(0, 0, &irq0); @@ -2025,7 +2025,7 @@ static int _disable_pit_irq(void(*hpet_broadcast_setup)(void)) return -1; /* - * If we do not rely on PIT CH0 then we can use HPET for one-shot timer + * If we do not rely on PIT CH0 then we can use HPET for one-shot timer * emulation when entering deep C states. * XXX dom0 may rely on RTC interrupt delivery, so only enable * hpet_broadcast if FSB mode available or if force_hpet_broadcast.