From patchwork Mon Aug 17 15:57:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Roger Pau Monne X-Patchwork-Id: 11718759 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B5A78109B for ; Mon, 17 Aug 2020 16:00:01 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B9A020885 for ; Mon, 17 Aug 2020 16:00:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="Ju688uKM" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8B9A020885 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=citrix.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1k7hXO-00077g-7h; Mon, 17 Aug 2020 15:59:06 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1k7hXN-00073P-3N for xen-devel@lists.xenproject.org; Mon, 17 Aug 2020 15:59:05 +0000 X-Inumbo-ID: 51b78f9d-fad0-4c41-a9e0-5c7261eb96e8 Received: from esa3.hc3370-68.iphmx.com (unknown [216.71.145.155]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 51b78f9d-fad0-4c41-a9e0-5c7261eb96e8; Mon, 17 Aug 2020 15:59:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1597679940; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F/Ls1vXs3JLCaDO3OMKs0GkvZz4YTpGo+BI7GjCWN+A=; b=Ju688uKMZP8oM6iW5pYVm6sT6VpHCOb6d/+jNCy0E6tygRBsYUDnhM3V LPhBCCtaeLzXd4EUmT1V9S1FMDk6nCx8huqfmqNFr9VXg/GcBC3XcK9qL qxqtcdPX3Ni2uluM9JzWeVx3aiFGI47EefBthoO30jhrvo5ylkVpsFWuE s=; Authentication-Results: esa3.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: OqmOhAaQ34hFtLweGTvGmfWDIiPIs06YVkYMJRpw6AFmKK0+l1Txm31nZnCnpQM9eVpSLo7Skb 0aXOrZAPGA411m/oYh8YdsWjiQPIIW/ZJZsFHZxcHpSed2tDJMb4Jh712xdb4yTzGvi9k/Q5X6 Ue9f8wyRs56iaQdwhT2M6ZsUXH2Wf4tv1CEWRq9PSQoCFbFkT303lbN/N8qheDf6RR+4w6ifAm hhenlmGVldRPNfPkMQphPMZwq1fGTwlJ21WQbQ6m+nke3V44SQOa6LChrQ/7vEq2IO4RgFtej5 XjI= X-SBRS: 2.7 X-MesageID: 24673333 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.76,324,1592884800"; d="scan'208";a="24673333" From: Roger Pau Monne To: CC: Roger Pau Monne , Jan Beulich , Andrew Cooper , Wei Liu Subject: [PATCH 5/8] x86/pv: allow reading APIC_BASE MSR Date: Mon, 17 Aug 2020 17:57:54 +0200 Message-ID: <20200817155757.3372-6-roger.pau@citrix.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200817155757.3372-1-roger.pau@citrix.com> References: <20200817155757.3372-1-roger.pau@citrix.com> MIME-Version: 1.0 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Linux PV guests will attempt to read the APIC_BASE MSR, so just report a default value to make Linux happy. Signed-off-by: Roger Pau Monné Acked-by: Andrew Cooper --- xen/arch/x86/pv/emul-priv-op.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index ff87c7d769..554a95ae8d 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -872,6 +872,13 @@ static int read_msr(unsigned int reg, uint64_t *val, switch ( reg ) { + case MSR_APIC_BASE: + /* Linux PV guests will attempt to read APIC_BASE. */ + *val = APIC_BASE_ENABLE | APIC_DEFAULT_PHYS_BASE; + if ( !curr->vcpu_id ) + *val |= APIC_BASE_BSP; + return X86EMUL_OKAY; + case MSR_FS_BASE: if ( is_pv_32bit_domain(currd) ) break;