From patchwork Thu Aug 20 15:08:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Roger Pau Monne X-Patchwork-Id: 11726497 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8158F739 for ; Thu, 20 Aug 2020 15:10:14 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5CACE208E4 for ; Thu, 20 Aug 2020 15:10:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="FLLQf6MN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5CACE208E4 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=citrix.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1k8mCR-0003zE-B7; Thu, 20 Aug 2020 15:09:55 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1k8mCQ-0003lg-2a for xen-devel@lists.xenproject.org; Thu, 20 Aug 2020 15:09:54 +0000 X-Inumbo-ID: 9b9d86af-17a7-4d72-a21f-c75d8547d178 Received: from esa5.hc3370-68.iphmx.com (unknown [216.71.155.168]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 9b9d86af-17a7-4d72-a21f-c75d8547d178; Thu, 20 Aug 2020 15:09:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1597936180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u63m2tXhuuAu/gd/zkG4g8sb+Z+3RgZGzbLxlSgXxBo=; b=FLLQf6MNAmDy3kbMwrc49GPRFtRK+OR72K5NZ5F/l1fXmfNDEpeRGPny 0euUCjH34cNgfmpDBoKqLo0L3T7JkrLVoOPm0KInOF01uRGJTF6x1c1AA bTdZEM9QZwxSPoGd0n6G6OeKdT9MihoF+KKJ4nj6TVuIY9caxPc1UFaOq E=; Authentication-Results: esa5.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: UE5O4/bvrPO/wv6B7XMDrVbV0sbAZ/kXCKUsOfw6/1lDaYcLKz2Sdy4k5yZr/ZSMdlcWtOl4iV qKor7pxl+zI/EYgrSrH7XTRTJ9w8bgZJvitq8wWnyxZQ0w0GKupz0kBuGAhELMASFCmp9G9KhT EOTfkpPKrzb5aGcxj1A2fQhMYmcAZBpwKSNY4Pt30sNbjG2qqj902Uo4RLUN6vlRqwGKInbdZ1 dZIThQ07DymCgvxh1PB6J5xHBE2zoqZjPAl1T5bJur2LwF3T79vbIJM3Hjqc3qw0ktsh2mOgEM yBI= X-SBRS: 2.7 X-MesageID: 25108129 X-Ironport-Server: esa5.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.76,333,1592884800"; d="scan'208";a="25108129" From: Roger Pau Monne To: CC: Andrew Cooper , Jan Beulich , Wei Liu , =?utf-8?q?Roger_Pau_?= =?utf-8?q?Monn=C3=A9?= Subject: [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd, wr}msr() Date: Thu, 20 Aug 2020 17:08:35 +0200 Message-ID: <20200820150835.27440-9-roger.pau@citrix.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200820150835.27440-1-roger.pau@citrix.com> References: <20200820150835.27440-1-roger.pau@citrix.com> MIME-Version: 1.0 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Andrew Cooper Now that the main PV/HVM MSR handlers raise #GP for all unknown MSRs, there is no need to special case these MSRs any more. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné --- Changes since v1: - New in this version. --- xen/arch/x86/msr.c | 46 ---------------------------------------------- 1 file changed, 46 deletions(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index bb0dd5ff0a..560719c2aa 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -159,29 +159,6 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) switch ( msr ) { - case MSR_AMD_PATCHLOADER: - case MSR_IA32_UCODE_WRITE: - case MSR_PRED_CMD: - case MSR_FLUSH_CMD: - /* Write-only */ - case MSR_TEST_CTRL: - case MSR_CORE_CAPABILITIES: - case MSR_TSX_FORCE_ABORT: - case MSR_TSX_CTRL: - case MSR_MCU_OPT_CTRL: - case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7): - case MSR_U_CET: - case MSR_S_CET: - case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: - case MSR_AMD64_LWP_CFG: - case MSR_AMD64_LWP_CBADDR: - case MSR_PPIN_CTL: - case MSR_PPIN: - case MSR_AMD_PPIN_CTL: - case MSR_AMD_PPIN: - /* Not offered to guests. */ - goto gp_fault; - case MSR_IA32_FEATURE_CONTROL: if ( !(cp->x86_vendor & X86_VENDOR_INTEL) ) goto gp_fault; @@ -349,29 +326,6 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) { uint64_t rsvd; - case MSR_IA32_PLATFORM_ID: - case MSR_CORE_CAPABILITIES: - case MSR_INTEL_CORE_THREAD_COUNT: - case MSR_INTEL_PLATFORM_INFO: - case MSR_ARCH_CAPABILITIES: - /* Read-only */ - case MSR_TEST_CTRL: - case MSR_TSX_FORCE_ABORT: - case MSR_TSX_CTRL: - case MSR_MCU_OPT_CTRL: - case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7): - case MSR_U_CET: - case MSR_S_CET: - case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: - case MSR_AMD64_LWP_CFG: - case MSR_AMD64_LWP_CBADDR: - case MSR_PPIN_CTL: - case MSR_PPIN: - case MSR_AMD_PPIN_CTL: - case MSR_AMD_PPIN: - /* Not offered to guests. */ - goto gp_fault; - case MSR_AMD_PATCHLEVEL: BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL); /*