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SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2020 03:28:54.3242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca215c0f-ac23-4983-29b4-08d847ddd404 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT020.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR08MB5317 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU FP/SIMD implementations. Currently, we exactly know the meaning of 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD features presented. If there is a value 0x2 bumped in the future, Xen behaviors for value <= 0x1 can also take effect. But what Xen done for value <= 0x1 may not always cover new value 0x2 required. We throw these messages to break the silence when Xen detected unknown FP/SIMD IDs to notice user to check. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis --- xen/arch/arm/setup.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 7968cee47d..c7802d0e49 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -99,6 +99,28 @@ static const char * __initdata processor_implementers[] = { ['i'] = "Intel Corporation", }; +static const char * __initdata fp_implements[] = { + "Floating-point", + "Floating-point + half-precision floating-point arithmetic", + "Floating-point Unknown ID 0x2", + "Floating-point Unknown ID 0x3", + "Floating-point Unknown ID 0x4", + "Floating-point Unknown ID 0x5", + "Floating-point Unknown ID 0x6", + "Floating-point Unknown ID 0x7", +}; + +static const char * __initdata advsimd_implements[] = { + "AdvancedSIMD", + "AdvancedSIMD + half-precision floating-point arithmetic", + "AdvancedSIMD Unknown ID 0x2", + "AdvancedSIMD Unknown ID 0x3", + "AdvancedSIMD Unknown ID 0x4", + "AdvancedSIMD Unknown ID 0x5", + "AdvancedSIMD Unknown ID 0x6", + "AdvancedSIMD Unknown ID 0x7", +}; + static void __init processor_id(void) { const char *implementer = "Unknown"; @@ -129,8 +151,8 @@ static void __init processor_id(void) cpu_has_el1_32 ? "64+32" : cpu_has_el1_64 ? "64" : "No", cpu_has_el0_32 ? "64+32" : cpu_has_el0_64 ? "64" : "No"); printk(" Extensions:%s%s%s\n", - cpu_has_fp ? " FloatingPoint" : "", - cpu_has_simd ? " AdvancedSIMD" : "", + cpu_has_fp ? fp_implements[boot_cpu_feature64(fp)] : "", + cpu_has_simd ? advsimd_implements[boot_cpu_feature64(simd)] : "", cpu_has_gicv3 ? " GICv3-SysReg" : ""); printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n",