diff mbox series

xen/iommu: smmu: Use 1UL << 31 rather than 1 << 31

Message ID 20201224152419.22453-1-julien@xen.org (mailing list archive)
State New, archived
Headers show
Series xen/iommu: smmu: Use 1UL << 31 rather than 1 << 31 | expand

Commit Message

Julien Grall Dec. 24, 2020, 3:24 p.m. UTC 
From: Julien Grall <jgrall@amazon.com>

Replace all the use of 1 << 31 with 1UL << 31 to prevent undefined
behavior in the SMMU driver.

Signed-off-by: Julien Grall <jgrall@amazon.com>
---
 xen/drivers/passthrough/arm/smmu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Hans van Kranenburg Dec. 24, 2020, 7:48 p.m. UTC | #1 
On 12/24/20 4:24 PM, Julien Grall wrote:
> From: Julien Grall <jgrall@amazon.com>
> 
> Replace all the use of 1 << 31 with 1UL << 31 to prevent undefined
> behavior in the SMMU driver.

You're replacing it by 1U, not 1UL, in the patch below.

Hans

> Signed-off-by: Julien Grall <jgrall@amazon.com>
> ---
>  xen/drivers/passthrough/arm/smmu.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c
> index ed04d85e05e9..3e8aa378669b 100644
> --- a/xen/drivers/passthrough/arm/smmu.c
> +++ b/xen/drivers/passthrough/arm/smmu.c
> @@ -405,7 +405,7 @@ static struct iommu_group *iommu_group_get(struct device *dev)
>  #define ID0_NUMSMRG_SHIFT		0
>  #define ID0_NUMSMRG_MASK		0xff
>  
> -#define ID1_PAGESIZE			(1 << 31)
> +#define ID1_PAGESIZE			(1U << 31)
>  #define ID1_NUMPAGENDXB_SHIFT		28
>  #define ID1_NUMPAGENDXB_MASK		7
>  #define ID1_NUMS2CB_SHIFT		16
> @@ -438,7 +438,7 @@ static struct iommu_group *iommu_group_get(struct device *dev)
>  
>  /* Stream mapping registers */
>  #define ARM_SMMU_GR0_SMR(n)		(0x800 + ((n) << 2))
> -#define SMR_VALID			(1 << 31)
> +#define SMR_VALID			(1U << 31)
>  #define SMR_MASK_SHIFT			16
>  #define SMR_MASK_MASK			0x7fff
>  #define SMR_ID_SHIFT			0
> @@ -506,7 +506,7 @@ static struct iommu_group *iommu_group_get(struct device *dev)
>  #define RESUME_RETRY			(0 << 0)
>  #define RESUME_TERMINATE		(1 << 0)
>  
> -#define TTBCR_EAE			(1 << 31)
> +#define TTBCR_EAE			(1U << 31)
>  
>  #define TTBCR_PASIZE_SHIFT		16
>  #define TTBCR_PASIZE_MASK		0x7
> @@ -562,7 +562,7 @@ static struct iommu_group *iommu_group_get(struct device *dev)
>  #define MAIR_ATTR_IDX_CACHE		1
>  #define MAIR_ATTR_IDX_DEV		2
>  
> -#define FSR_MULTI			(1 << 31)
> +#define FSR_MULTI			(1U << 31)
>  #define FSR_SS				(1 << 30)
>  #define FSR_UUT				(1 << 8)
>  #define FSR_ASF				(1 << 7)
>
Jan Beulich Jan. 4, 2021, 2:21 p.m. UTC | #2 
On 24.12.2020 16:24, Julien Grall wrote:
> From: Julien Grall <jgrall@amazon.com>
> 
> Replace all the use of 1 << 31 with 1UL << 31 to prevent undefined
> behavior in the SMMU driver.
> 
> Signed-off-by: Julien Grall <jgrall@amazon.com>

With, as already pointed out by Hans, 1UL replaced by 1U in
title and description
Reviewed-by: Jan Beulich <jbeulich@suse.com>

Jan
Julien Grall Jan. 13, 2021, 5:50 p.m. UTC | #3 
Hi Hans,

Sorry for the late reply.

On 24/12/2020 19:48, Hans van Kranenburg wrote:
> On 12/24/20 4:24 PM, Julien Grall wrote:
>> From: Julien Grall <jgrall@amazon.com>
>>
>> Replace all the use of 1 << 31 with 1UL << 31 to prevent undefined
>> behavior in the SMMU driver.
> 
> You're replacing it by 1U, not 1UL, in the patch below.

Thank you for pointing that out! Stefano fixed it on commit.

Cheers,
diff mbox series

Patch

diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c
index ed04d85e05e9..3e8aa378669b 100644
--- a/xen/drivers/passthrough/arm/smmu.c
+++ b/xen/drivers/passthrough/arm/smmu.c
@@ -405,7 +405,7 @@  static struct iommu_group *iommu_group_get(struct device *dev)
 #define ID0_NUMSMRG_SHIFT		0
 #define ID0_NUMSMRG_MASK		0xff
 
-#define ID1_PAGESIZE			(1 << 31)
+#define ID1_PAGESIZE			(1U << 31)
 #define ID1_NUMPAGENDXB_SHIFT		28
 #define ID1_NUMPAGENDXB_MASK		7
 #define ID1_NUMS2CB_SHIFT		16
@@ -438,7 +438,7 @@  static struct iommu_group *iommu_group_get(struct device *dev)
 
 /* Stream mapping registers */
 #define ARM_SMMU_GR0_SMR(n)		(0x800 + ((n) << 2))
-#define SMR_VALID			(1 << 31)
+#define SMR_VALID			(1U << 31)
 #define SMR_MASK_SHIFT			16
 #define SMR_MASK_MASK			0x7fff
 #define SMR_ID_SHIFT			0
@@ -506,7 +506,7 @@  static struct iommu_group *iommu_group_get(struct device *dev)
 #define RESUME_RETRY			(0 << 0)
 #define RESUME_TERMINATE		(1 << 0)
 
-#define TTBCR_EAE			(1 << 31)
+#define TTBCR_EAE			(1U << 31)
 
 #define TTBCR_PASIZE_SHIFT		16
 #define TTBCR_PASIZE_MASK		0x7
@@ -562,7 +562,7 @@  static struct iommu_group *iommu_group_get(struct device *dev)
 #define MAIR_ATTR_IDX_CACHE		1
 #define MAIR_ATTR_IDX_DEV		2
 
-#define FSR_MULTI			(1 << 31)
+#define FSR_MULTI			(1U << 31)
 #define FSR_SS				(1 << 30)
 #define FSR_UUT				(1 << 8)
 #define FSR_ASF				(1 << 7)