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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.onmicrosoft.com; s=selector2-citrix-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Blm/0Bd7WSGIeDuYXRMAPB5HSkKSVJuxKVDttIrYYCg=; b=ck3d6o4ZCj7tLxrgbrYwNUpew2URpTntyP9ahfroDKOb/DQnjSLnTv+sjy3s4f4i8WoS52JIWygoPpd987crw4Wy9qm0KrzAtGa1oQLS3lWEae1S8vWZDUXWti6pgOSualiSmDScpTu8kD24IZ1/vGsh7UpLAZBIL1svJPkmG0g= From: Roger Pau Monne To: CC: Andrew Cooper , Roger Pau Monne , Ian Jackson , Wei Liu , Anthony PERARD Subject: [PATCH 15/21] libs/guest: obtain a compatible cpu policy from two input ones Date: Tue, 23 Mar 2021 10:58:43 +0100 Message-ID: <20210323095849.37858-16-roger.pau@citrix.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210323095849.37858-1-roger.pau@citrix.com> References: <20210323095849.37858-1-roger.pau@citrix.com> X-ClientProxiedBy: MR2P264CA0109.FRAP264.PROD.OUTLOOK.COM (2603:10a6:500:33::25) To DS7PR03MB5608.namprd03.prod.outlook.com (2603:10b6:5:2c9::18) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9c6c3518-4f3d-4d3f-f189-08d8ede2913c X-MS-TrafficTypeDiagnostic: DM6PR03MB4969: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?LKwC1iCJ8uYSQYO3wtw846QHXGs5o7?= =?utf-8?q?tZSrN1U/5kYJxbEim2PoLt5rXuvQ2dNUDAxBzIVfBLLlMvh5cG3d/fLXhwYaWKNlY?= =?utf-8?q?HzTrfJBHDU5e4TsEqz9OY8ncBt6gpjVlMZbp6zJV1Q+o3EFoBaf8Mv2uTSP7sZDOh?= =?utf-8?q?SG0Iui7D2H2LpZTHd42o0ZyF0MZwYGUKS1Vm8IE0vn2ohtRl5ua5x79179/scju6z?= =?utf-8?q?cgZRXzjqyJw4uZa85Q+2M/ihgeRPmU1KrDIPb8/dVYztJaWg7IvzJ/rYvgC4m9Pyo?= =?utf-8?q?XZ0aw9fJx9AXD5QUYL22hCi1UNDESip0uOqjWzv28n3jopOoSKzJ9p6uUWHCJKKBt?= =?utf-8?q?DvNRQIaziIZQjl+UMfN1JQULzEfz6nlDQF6mlQW2RwJr1jgtdUexgC1B3us9RmQpK?= =?utf-8?q?GfDwKES17RB6KN9OP6YlsauKj+x/aQcepPO29swbpy2mEoUPkd8UyzHqFCFwuOben?= =?utf-8?q?9L+IsIOtknFQU9GsjG8jLsVDADa6nSauwly4fDUldcU7tWj0KKN7cfPME+407RAUY?= =?utf-8?q?K0vXNbBpjJbcsQ1lVu80zZrp7eDQNLG9RnUmBh9e5Xe0mdUJLPtuiQrPv1s85E4ry?= =?utf-8?q?+bsVPhO3z7hUefl92qQmvWTIXcvQvS6LtkK1tKtLMv+ELJOPizumqPgvTjlxsCY4f?= =?utf-8?q?0S2mdmim1s1PqEFyXcPpjWbzFezIfNz2IHKew9/CvTu9PGuaFCELu5EcE+3P2nYeD?= =?utf-8?q?W6U2OKGu6fKZ5UnIXHx5/PQ7mAO1BPXtjlU25F7+mKSQZ7amsYFUDx1en+HnZ3Jqv?= =?utf-8?q?Qu6cfzwkKmqrYCqHz5jDsomJcrEGIxbIChSXEh73Py1Dcs+GSWmmxqls+sIbihu1N?= =?utf-8?q?vLgVJSPCpHhEH4dHX0biXLxq5OCkoWuasn1r9hkkmgh5A6qOqVJ+dDz1B894eHAO+?= =?utf-8?q?TW4HK0qIHY4e665UPBLmXTFdJ4B6quxh2qyc0ihenxrWLR861TWHiC2aJ68GNTlQf?= =?utf-8?q?GzUKarDeFlihZHSwUxXlkph9k51qylsVtnrl3I8MO+058EbHXmSLna4uxfNDfp4fE?= =?utf-8?q?bFs1tCHcO3KALXTiB1yzf2rRKafTmTjmLuN1DZEhVEYT/adYSsu23XMwiMu1+14h3?= =?utf-8?q?tYQ9VkAZHVArvFdtreTgqyLPBH93IbzAER6+ZC4HCDamJxs5b9HptqJbAAaot2e6m?= =?utf-8?q?tF7/HpatezKEtI/mVC6wm+rHSvRwNqIssL3AKEfKH4W0RKZidnyU8dyWcLN4+SVp2?= =?utf-8?q?/fI2LmHs5fS3Ep/E0LfyWbrpxx2ogkNnM5QJOhKQ2Zof/etTs/ixJliBRQqr+jHCF?= =?utf-8?q?bv47wJny3rq5XW?= X-MS-Exchange-CrossTenant-Network-Message-Id: 9c6c3518-4f3d-4d3f-f189-08d8ede2913c X-MS-Exchange-CrossTenant-AuthSource: DS7PR03MB5608.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2021 10:01:02.9122 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AmBkQTDaZgYjvGrZzSZcRLwEcJRHNbMFH99lfS0ltQcX9GYSgV6GcICqwk8W0nZyu5IYAZGAHKIYnAHXV+jKww== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR03MB4969 X-OriginatorOrg: citrix.com Introduce a helper to obtain a compatible cpu policy based on two input cpu policies. Currently this is done by and'ing all CPUID leaves and MSR entries, except for MSR_ARCH_CAPABILITIES which has the RSBA bit or'ed. The _AC macro is pulled from libxl_internal.h into xen-tools/libs.h since it's required in order to use the msr-index.h header. Note there's no need to place this helper in libx86, since the calculation of a compatible policy shouldn't be done from the hypervisor. No callers of the interface introduced. Signed-off-by: Roger Pau Monné --- tools/include/xen-tools/libs.h | 5 ++ tools/include/xenctrl.h | 4 ++ tools/libs/guest/xg_cpuid_x86.c | 115 ++++++++++++++++++++++++++++++ tools/libs/light/libxl_internal.h | 2 - 4 files changed, 124 insertions(+), 2 deletions(-) diff --git a/tools/include/xen-tools/libs.h b/tools/include/xen-tools/libs.h index a16e0c38070..b9e89f9a711 100644 --- a/tools/include/xen-tools/libs.h +++ b/tools/include/xen-tools/libs.h @@ -63,4 +63,9 @@ #define ROUNDUP(_x,_w) (((unsigned long)(_x)+(1UL<<(_w))-1) & ~((1UL<<(_w))-1)) #endif +#ifndef _AC +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#endif + #endif /* __XEN_TOOLS_LIBS__ */ diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h index 165beff330f..5f3e5e17e9d 100644 --- a/tools/include/xenctrl.h +++ b/tools/include/xenctrl.h @@ -2622,6 +2622,10 @@ int xc_cpu_policy_update_msrs(xc_interface *xch, xc_cpu_policy_t policy, /* Compatibility calculations. */ bool xc_cpu_policy_is_compatible(xc_interface *xch, const xc_cpu_policy_t p1, const xc_cpu_policy_t p2); +int xc_cpu_policy_calc_compatible(xc_interface *xch, + const xc_cpu_policy_t p1, + const xc_cpu_policy_t p2, + xc_cpu_policy_t out); int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps); int xc_get_cpu_featureset(xc_interface *xch, uint32_t index, diff --git a/tools/libs/guest/xg_cpuid_x86.c b/tools/libs/guest/xg_cpuid_x86.c index 30ea02a0f31..4afca3249ba 100644 --- a/tools/libs/guest/xg_cpuid_x86.c +++ b/tools/libs/guest/xg_cpuid_x86.c @@ -32,6 +32,7 @@ enum { #include }; +#include #include #include @@ -1115,3 +1116,117 @@ bool xc_cpu_policy_is_compatible(xc_interface *xch, const xc_cpu_policy_t p1, return false; } + +static uint64_t level_msr(unsigned int index, uint64_t val1, uint64_t val2) +{ + uint64_t val; + + switch( index ) + { + case MSR_ARCH_CAPABILITIES: + val = val1 & val2; + /* + * Set RSBA if present on any of the input values to notice the guest + * might run on vulnerable hardware at some point. + */ + val |= (val1 | val2) & ARCH_CAPS_RSBA; + break; + + default: + val = val1 & val2; + break; + } + + return val; +} + +int xc_cpu_policy_calc_compatible(xc_interface *xch, + const xc_cpu_policy_t p1, + const xc_cpu_policy_t p2, + xc_cpu_policy_t out) +{ + xen_cpuid_leaf_t *leaves = NULL, *p1_leaves = NULL, *p2_leaves = NULL; + xen_msr_entry_t *msrs = NULL, *p1_msrs = NULL, *p2_msrs = NULL; + unsigned int nr_leaves, nr_msrs, i, j, index; + unsigned int p1_nr_leaves, p1_nr_msrs, p2_nr_leaves, p2_nr_msrs; + int rc; + + if ( xc_cpu_policy_get_size(xch, &nr_leaves, &nr_msrs) ) + { + PERROR("Failed to obtain policy info size"); + return -1; + } + + leaves = calloc(nr_leaves, sizeof(*leaves)); + p1_leaves = calloc(nr_leaves, sizeof(*p1_leaves)); + p2_leaves = calloc(nr_leaves, sizeof(*p2_leaves)); + msrs = calloc(nr_msrs, sizeof(*msrs)); + p1_msrs = calloc(nr_msrs, sizeof(*p1_msrs)); + p2_msrs = calloc(nr_msrs, sizeof(*p2_msrs)); + + p1_nr_leaves = p2_nr_leaves = nr_leaves; + p1_nr_msrs = p2_nr_msrs = nr_msrs; + + if ( !leaves || !p1_leaves || !p2_leaves || + !msrs || !p1_msrs || !p2_msrs ) + { + ERROR("Failed to allocate resources"); + errno = ENOMEM; + rc = -1; + goto out; + } + + rc = xc_cpu_policy_serialise(xch, p1, p1_leaves, &p1_nr_leaves, + p1_msrs, &p1_nr_msrs); + if ( rc ) + goto out; + rc = xc_cpu_policy_serialise(xch, p2, p2_leaves, &p2_nr_leaves, + p2_msrs, &p2_nr_msrs); + if ( rc ) + goto out; + + index = 0; + for ( i = 0; i < p1_nr_leaves; i++ ) + for ( j = 0; j < p2_nr_leaves; j++ ) + if ( p1_leaves[i].leaf == p2_leaves[j].leaf && + p1_leaves[i].subleaf == p2_leaves[j].subleaf ) + { + leaves[index].leaf = p1_leaves[i].leaf; + leaves[index].subleaf = p1_leaves[i].subleaf; + leaves[index].a = p1_leaves[i].a & p2_leaves[j].a; + leaves[index].b = p1_leaves[i].b & p2_leaves[j].b; + leaves[index].c = p1_leaves[i].c & p2_leaves[j].c; + leaves[index].d = p1_leaves[i].d & p2_leaves[j].d; + index++; + } + nr_leaves = index; + + index = 0; + for ( i = 0; i < p1_nr_msrs; i++ ) + for ( j = 0; j < p2_nr_msrs; j++ ) + if ( p1_msrs[i].idx == p2_msrs[j].idx ) + { + msrs[index].idx = p1_msrs[i].idx; + msrs[index].val = level_msr(p1_msrs[i].idx, + p1_msrs[i].val, p2_msrs[j].val); + index++; + } + nr_msrs = index; + + rc = deserialize_policy(xch, out, nr_leaves, leaves, nr_msrs, msrs); + if ( rc ) + { + errno = -rc; + rc = -1; + } + + out: + free(leaves); + free(p1_leaves); + free(p2_leaves); + free(msrs); + free(p1_msrs); + free(p2_msrs); + + return rc; +} diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_internal.h index 22b1775b752..53b8939fb5a 100644 --- a/tools/libs/light/libxl_internal.h +++ b/tools/libs/light/libxl_internal.h @@ -126,8 +126,6 @@ #define PVSHIM_CMDLINE "pv-shim console=xen,pv" /* Size macros. */ -#define __AC(X,Y) (X##Y) -#define _AC(X,Y) __AC(X,Y) #define MB(_mb) (_AC(_mb, ULL) << 20) #define GB(_gb) (_AC(_gb, ULL) << 30)