From patchwork Mon Jul 12 08:53:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Orzel X-Patchwork-Id: 12370575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88E2DC07E99 for ; Mon, 12 Jul 2021 08:53:46 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4F15260FF0 for ; Mon, 12 Jul 2021 08:53:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4F15260FF0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.154434.285381 (Exim 4.92) (envelope-from ) id 1m2rh5-0007eg-3v; Mon, 12 Jul 2021 08:53:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 154434.285381; Mon, 12 Jul 2021 08:53:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1m2rh5-0007eZ-0R; Mon, 12 Jul 2021 08:53:39 +0000 Received: by outflank-mailman (input) for mailman id 154434; Mon, 12 Jul 2021 08:53:37 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1m2rh3-0007eN-5K for xen-devel@lists.xenproject.org; Mon, 12 Jul 2021 08:53:37 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id a4ddd3ae-e2ee-11eb-86d8-12813bfff9fa; Mon, 12 Jul 2021 08:53:36 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB3261FB; Mon, 12 Jul 2021 01:53:35 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.1.228]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C07FC3F694; Mon, 12 Jul 2021 01:53:34 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a4ddd3ae-e2ee-11eb-86d8-12813bfff9fa From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v3] xen/arm64: Remove READ/WRITE_SYSREG32 helper macros Date: Mon, 12 Jul 2021 10:53:29 +0200 Message-Id: <20210712085329.16613-1-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. The last place in code making use of READ/WRITE_SYSREG32 on arm64 is in TVM_REG macro defining functions vreg_emulate_. Implement a macro WRITE_SYSREG_SZ which expands as follows: -on arm64: WRITE_SYSREG -on arm32: WRITE_SYSREG{32/64} As there are no other places in the code using these helpers on arm64 - remove them. Signed-off-by: Michal Orzel Reviewed-by: Bertrand Marquis --- Changes since v2: -add uint##sz##_t casting Changes since v1: -implement WRITE_SYSREG_SZ instead of duplicating the TVM_REG --- xen/arch/arm/vcpreg.c | 12 +++++++++++- xen/include/asm-arm/arm64/sysregs.h | 4 ---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index f0cdcc8a54..e3ce56d875 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -47,6 +47,16 @@ * */ +#ifdef CONFIG_ARM_64 +#define WRITE_SYSREG_SZ(sz, val, sysreg) WRITE_SYSREG((uint##sz##_t)val, sysreg) +#else +/* + * WRITE_SYSREG{32/64} on arm32 is defined as variadic macro which imposes + * on the below macro to be defined like that as well. + */ +#define WRITE_SYSREG_SZ(sz, val, sysreg...) WRITE_SYSREG##sz(val, sysreg) +#endif + /* The name is passed from the upper macro to workaround macro expansion. */ #define TVM_REG(sz, func, reg...) \ static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) \ @@ -55,7 +65,7 @@ static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) \ bool cache_enabled = vcpu_has_cache_enabled(v); \ \ GUEST_BUG_ON(read); \ - WRITE_SYSREG##sz(*r, reg); \ + WRITE_SYSREG_SZ(sz, *r, reg); \ \ p2m_toggle_cache(v, cache_enabled); \ \ diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index 077fd95fb7..795901e1ba 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -87,10 +87,6 @@ /* Access to system registers */ -#define READ_SYSREG32(name) ((uint32_t)READ_SYSREG64(name)) - -#define WRITE_SYSREG32(v, name) WRITE_SYSREG64((uint64_t)v, name) - #define WRITE_SYSREG64(v, name) do { \ uint64_t _r = v; \ asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \