diff mbox series

[3/7] xen/arm: head: Add missing isb after writing to SCTLR_EL2/HSCTLR

Message ID 20220624091146.35716-4-julien@xen.org (mailing list archive)
State Superseded
Headers show
Series xen/arm: mm: Bunch of clean-ups | expand

Commit Message

Julien Grall June 24, 2022, 9:11 a.m. UTC
From: Julien Grall <jgrall@amazon.com>

Write to SCTLR_EL2/HSCTLR may not be visible until the next context
synchronization. When initializing the CPU, we want the update to take
effect right now. So add an isb afterwards.

Spec references:
    - AArch64: D13.1.2 ARM DDI 0406C.d
    - AArch32 v8: G8.1.2 ARM DDI 0406C.d
    - AArch32 v7: B5.6.3 ARM DDI 0406C.d

Signed-off-by: Julien Grall <jgrall@amazon.com>
---
 xen/arch/arm/arm32/head.S | 1 +
 xen/arch/arm/arm64/head.S | 1 +
 2 files changed, 2 insertions(+)

Comments

Michal Orzel June 27, 2022, 6:36 a.m. UTC | #1
Hi Julien,

On 24.06.2022 11:11, Julien Grall wrote:
> From: Julien Grall <jgrall@amazon.com>
> 
> Write to SCTLR_EL2/HSCTLR may not be visible until the next context
> synchronization. When initializing the CPU, we want the update to take
> effect right now. So add an isb afterwards.
> 
> Spec references:
>     - AArch64: D13.1.2 ARM DDI 0406C.d
>     - AArch32 v8: G8.1.2 ARM DDI 0406C.d
>     - AArch32 v7: B5.6.3 ARM DDI 0406C.d
> 
> Signed-off-by: Julien Grall <jgrall@amazon.com>
Reviewed-by: Michal Orzel <michal.orzel@arm.com>

Cheers,
Michal
Bertrand Marquis June 27, 2022, 2 p.m. UTC | #2
Hi Julien,

> On 24 Jun 2022, at 10:11, Julien Grall <julien@xen.org> wrote:
> 
> From: Julien Grall <jgrall@amazon.com>
> 
> Write to SCTLR_EL2/HSCTLR may not be visible until the next context
> synchronization. When initializing the CPU, we want the update to take
> effect right now. So add an isb afterwards.
> 
> Spec references:
>    - AArch64: D13.1.2 ARM DDI 0406C.d
>    - AArch32 v8: G8.1.2 ARM DDI 0406C.d
>    - AArch32 v7: B5.6.3 ARM DDI 0406C.d
> 
> Signed-off-by: Julien Grall <jgrall@amazon.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>

Cheers
Bertrand
diff mbox series

Patch

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 77f0a619ca51..98ccf18b51f1 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -353,6 +353,7 @@  cpu_init_done:
 
         ldr   r0, =HSCTLR_SET
         mcr   CP32(r0, HSCTLR)
+        isb
 
         mov   pc, r5                        /* Return address is in r5 */
 ENDPROC(cpu_init)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 109ae7de0c2b..1babcc65d7c9 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -486,6 +486,7 @@  cpu_init:
 
         ldr   x0, =SCTLR_EL2_SET
         msr   SCTLR_EL2, x0
+        isb
 
         /*
          * Ensure that any exceptions encountered at EL2