From patchwork Tue Dec 20 08:50:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13077638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79EA2C3DA79 for ; Tue, 20 Dec 2022 08:51:27 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.466594.725515 (Exim 4.92) (envelope-from ) id 1p7YLG-0002GN-UP; Tue, 20 Dec 2022 08:51:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 466594.725515; Tue, 20 Dec 2022 08:51:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p7YLG-0002GG-R1; Tue, 20 Dec 2022 08:51:18 +0000 Received: by outflank-mailman (input) for mailman id 466594; Tue, 20 Dec 2022 08:51:17 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p7YLE-0001kV-Ve for xen-devel@lists.xenproject.org; Tue, 20 Dec 2022 08:51:16 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id 76185c53-8043-11ed-91b6-6bf2151ebd3b; Tue, 20 Dec 2022 09:51:15 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 15A56FEC; Tue, 20 Dec 2022 00:51:56 -0800 (PST) Received: from e125770.cambridge.arm.com (e125770.cambridge.arm.com [10.1.195.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 40C9A3F71A; Tue, 20 Dec 2022 00:51:14 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 76185c53-8043-11ed-91b6-6bf2151ebd3b From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: wei.chen@arm.com, Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [RFC PATCH 02/18] arm: cppcheck: misra rule 20.7 deviation on processor.h Date: Tue, 20 Dec 2022 08:50:44 +0000 Message-Id: <20221220085100.22848-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221220085100.22848-1-luca.fancellu@arm.com> References: <20221220085100.22848-1-luca.fancellu@arm.com> Cppcheck has found a violation of rule 20.7 for the macro __DECL_REG, but the macro parameters are never used as an expression, they are used for text substitution and adding parenthesis would break the code. Cppcheck is not taking into account the context of use of the macro argument, so we can suppress the finding. Eclair and coverity does not report this finding. Signed-off-by: Luca Fancellu --- xen/arch/arm/include/asm/arm64/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/arm64/processor.h b/xen/arch/arm/include/asm/arm64/processor.h index c749f80ad91b..aacbe5d4d538 100644 --- a/xen/arch/arm/include/asm/arm64/processor.h +++ b/xen/arch/arm/include/asm/arm64/processor.h @@ -4,7 +4,7 @@ #ifndef __ASSEMBLY__ /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ - +/* SAF-1-false-positive-cppcheck R20.7 argument as text substitution */ #define __DECL_REG(n64, n32) union { \ uint64_t n64; \ uint32_t n32; \