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Tsirkin" , Paolo Bonzini , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Chuck Zmudzinski , Bernhard Beschow Subject: [PATCH v2 4/6] hw/isa/piix: Avoid Xen-specific variant of piix_write_config() Date: Wed, 4 Jan 2023 15:44:35 +0100 Message-Id: <20230104144437.27479-5-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230104144437.27479-1-shentey@gmail.com> References: <20230104144437.27479-1-shentey@gmail.com> MIME-Version: 1.0 Subscribe to pci_bus_fire_intx_routing_notifier() instead which allows for having a common piix_write_config() for all PIIX device models. While at it, move the subscription into machine code in order to resolve TYPE_PIIX3_XEN_DEVICE. In a possible future followup, pci_bus_fire_intx_routing_notifier() could be adjusted in such a way that subscribing to it doesn't require knowledge of the device firing it. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 18 ++++++++++++++++++ hw/isa/piix.c | 22 +--------------------- 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 792dcd3ce8..5738d9cdca 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -86,6 +86,21 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) return (pci_intx + slot_addend) & 3; } +static void piix_intx_routing_notifier_xen(PCIDevice *dev) +{ + int i; + + /* Scan for updates to PCI link routes (0x60-0x63). */ + for (i = 0; i < PIIX_NUM_PIRQS; i++) { + uint8_t v = dev->config_read(dev, PIIX_PIRQCA + i, 1); + if (v & 0x80) { + v = 0; + } + v &= 0xf; + xen_set_pci_link_route(i, v); + } +} + /* PC hardware initialisation */ static void pc_init1(MachineState *machine, const char *host_type, const char *pci_type) @@ -248,6 +263,9 @@ static void pc_init1(MachineState *machine, pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); if (xen_enabled()) { + pci_device_set_intx_routing_notifier( + pci_dev, piix_intx_routing_notifier_xen); + /* * Xen supports additional interrupt routes from the PCI devices to * the IOAPIC: the four pins of each PCI device on the bus are also diff --git a/hw/isa/piix.c b/hw/isa/piix.c index ac04781f46..d4cdb3dadb 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -125,26 +125,6 @@ static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val, } } -static void piix3_write_config_xen(PCIDevice *dev, - uint32_t address, uint32_t val, int len) -{ - int i; - - /* Scan for updates to PCI link routes (0x60-0x63). */ - for (i = 0; i < len; i++) { - uint8_t v = (val >> (8 * i)) & 0xff; - if (v & 0x80) { - v = 0; - } - v &= 0xf; - if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) { - xen_set_pci_link_route(address + i - PIIX_PIRQCA, v); - } - } - - piix_write_config(dev, address, val, len); -} - static void piix_reset(DeviceState *dev) { PIIXState *d = PIIX_PCI_DEVICE(dev); @@ -490,7 +470,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->config_write = piix3_write_config_xen; + k->config_write = piix_write_config; k->realize = piix3_realize; /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;