From patchwork Fri Jan 13 10:11:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13100426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B660CC677F1 for ; Fri, 13 Jan 2023 10:11:52 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.477048.739579 (Exim 4.92) (envelope-from ) id 1pGH2F-0004A7-Ts; Fri, 13 Jan 2023 10:11:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 477048.739579; Fri, 13 Jan 2023 10:11:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pGH2F-00049y-QW; Fri, 13 Jan 2023 10:11:43 +0000 Received: by outflank-mailman (input) for mailman id 477048; Fri, 13 Jan 2023 10:11:42 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pGH2E-0003t1-Eo for xen-devel@lists.xenproject.org; Fri, 13 Jan 2023 10:11:42 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pGH2E-0006d1-3y; Fri, 13 Jan 2023 10:11:42 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1pGH2D-0005Ty-Rv; Fri, 13 Jan 2023 10:11:42 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=vzfTzczjLXV/PEg7iDoDX2AUbfuIDhGYbEkSsXpjSeE=; b=CTJBH7q+3tEciLNn32G6x2pXxh v7WFKd3NEiPWlcGbm5f5hXiAs+5kZBGlPmpt4OHD2dQ5i01kl1uVLr6RLXw2gNlSFpZV6vJvqON8B DEuBa1JY11p3Og8QqrJ90ogMAeJKUT9LkfpLCyqQgdad2QrArUn3iWit5t8QDS3DtDeM=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Michal Orzel Subject: [PATCH v4 02/14] xen/arm64: flushtlb: Implement the TLBI repeat workaround for TLB flush by VA Date: Fri, 13 Jan 2023 10:11:24 +0000 Message-Id: <20230113101136.479-3-julien@xen.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113101136.479-1-julien@xen.org> References: <20230113101136.479-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Looking at the Neoverse N1 errata document, it is not clear to me why the TLBI repeat workaround is not applied for TLB flush by VA. The TBL flush by VA helpers are used in flush_xen_tlb_range_va_local() and flush_xen_tlb_range_va(). So if the range size if a fixed size smaller than a PAGE_SIZE, it would be possible that the compiler remove the loop and therefore replicate the sequence described in the erratum 1286807. So the TLBI repeat workaround should also be applied for the TLB flush by VA helpers. Fixes: 22e323d115d8 ("xen/arm: Add workaround for Cortex-A76/Neoverse-N1 erratum #1286807") Signed-off-by: Julien Grall Reviewed-by: Michal Orzel ---- This was spotted while looking at reducing the scope of the memory barriers. I don't have any HW affected. Changes in v4: - Add Michal's reviewed-by tag Changes in v3: - Patch added Tested-by: Henry Wang --- xen/arch/arm/include/asm/arm64/flushtlb.h | 31 +++++++++++++++++------ 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/include/asm/arm64/flushtlb.h index a40693b08dd3..7f81cbbb93f9 100644 --- a/xen/arch/arm/include/asm/arm64/flushtlb.h +++ b/xen/arch/arm/include/asm/arm64/flushtlb.h @@ -44,6 +44,27 @@ static inline void name(void) \ : : : "memory"); \ } +/* + * FLush TLB by VA. This will likely be used in a loop, so the caller + * is responsible to use the appropriate memory barriers before/after + * the sequence. + * + * See above about the ARM64_WORKAROUND_REPEAT_TLBI sequence. + */ +#define TLB_HELPER_VA(name, tlbop) \ +static inline void name(vaddr_t va) \ +{ \ + asm volatile( \ + "tlbi " # tlbop ", %0;" \ + ALTERNATIVE( \ + "nop; nop;", \ + "dsb ish;" \ + "tlbi " # tlbop ", %0;", \ + ARM64_WORKAROUND_REPEAT_TLBI, \ + CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ + : : "r" (va >> PAGE_SHIFT) : "memory"); \ +} + /* Flush local TLBs, current VMID only. */ TLB_HELPER(flush_guest_tlb_local, vmalls12e1, nsh); @@ -60,16 +81,10 @@ TLB_HELPER(flush_all_guests_tlb, alle1is, ish); TLB_HELPER(flush_xen_tlb_local, alle2, nsh); /* Flush TLB of local processor for address va. */ -static inline void __flush_xen_tlb_one_local(vaddr_t va) -{ - asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); -} +TLB_HELPER_VA(__flush_xen_tlb_one_local, vae2); /* Flush TLB of all processors in the inner-shareable domain for address va. */ -static inline void __flush_xen_tlb_one(vaddr_t va) -{ - asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); -} +TLB_HELPER_VA(__flush_xen_tlb_one, vae2is); #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */ /*