| Message ID | 20230113101136.479-9-julien@xen.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | xen/arm: Don't switch TTBR while the MMU is on | expand |
On 13/01/2023 11:11, Julien Grall wrote: > > > From: Julien Grall <jgrall@amazon.com> > > The sequence for flushing the TLBs is 4 instruction long and often > requires an explanation how it works. > > So create a helper and use it in the boot code (switch_ttbr() is left > alone until we decide the semantic of the call). > > Note that in secondary_switched, we were also flushing the instruction > cache and branch predictor. Neither of them was necessary because: > * We are only supporting IVIPT cache on arm32, so the instruction > cache flush is only necessary when executable code is modified. > None of the boot code is doing that. > * The instruction cache is not invalidated and misprediction is not > a problem at boot. > > Signed-off-by: Julien Grall <jgrall@amazon.com> > > ---- > Changes in v4: > - Expand the commit message to explain why switch_ttbr() is > not updated. > - Remove extra spaces in the comment > - Fix typo in the commit message Thanks, Reviewed-by: Michal Orzel <michal.orzel@amd.com> ~Michal
Hi Julien, > -----Original Message----- > Subject: [PATCH v4 08/14] xen/arm32: head: Introduce an helper to flush the > TLBs > > From: Julien Grall <jgrall@amazon.com> > > The sequence for flushing the TLBs is 4 instruction long and often > requires an explanation how it works. > > So create a helper and use it in the boot code (switch_ttbr() is left > alone until we decide the semantic of the call). > > Note that in secondary_switched, we were also flushing the instruction > cache and branch predictor. Neither of them was necessary because: > * We are only supporting IVIPT cache on arm32, so the instruction > cache flush is only necessary when executable code is modified. > None of the boot code is doing that. > * The instruction cache is not invalidated and misprediction is not > a problem at boot. > > Signed-off-by: Julien Grall <jgrall@amazon.com> Reviewed-by: Henry Wang <Henry.Wang@arm.com> I've also tested this patch on FVP in arm32 execution mode, and this patch is good, so: Tested-by: Henry Wang <Henry.Wang@arm.com> Kind regards, Henry
diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 50ad6c948be2..67b910808b74 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -66,6 +66,20 @@ add \rb, \rb, r10 .endm +/* + * Flush local TLBs + * + * @tmp: Scratch register + * + * See asm/arm32/flushtlb.h for the explanation of the sequence. + */ +.macro flush_xen_tlb_local tmp + dsb nshst + mcr CP32(\tmp, TLBIALLH) + dsb nsh + isb +.endm + /* * Common register usage in this file: * r0 - @@ -232,11 +246,7 @@ secondary_switched: mcrr CP64(r4, r5, HTTBR) dsb isb - mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ - mcr CP32(r0, ICIALLU) /* Flush I-cache */ - mcr CP32(r0, BPIALL) /* Flush branch predictor */ - dsb /* Ensure completion of TLB+BP flush */ - isb + flush_xen_tlb_local r0 #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ @@ -529,8 +539,7 @@ enable_mmu: * The state of the TLBs is unknown before turning on the MMU. * Flush them to avoid stale one. */ - mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLBs */ - dsb nsh + flush_xen_tlb_local r0 /* Write Xen's PT's paddr into the HTTBR */ load_paddr r0, boot_pgtable @@ -605,12 +614,7 @@ remove_identity_mapping: strd r2, r3, [r0, r1] identity_mapping_removed: - /* See asm/arm32/flushtlb.h for the explanation of the sequence. */ - dsb nshst - mcr CP32(r0, TLBIALLH) - dsb nsh - isb - + flush_xen_tlb_local r0 mov pc, lr ENDPROC(remove_identity_mapping)