From patchwork Fri May 26 11:06:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13256777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 676B6C7EE31 for ; Fri, 26 May 2023 11:07:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.540061.841540 (Exim 4.92) (envelope-from ) id 1q2VIN-0007gb-1E; Fri, 26 May 2023 11:07:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 540061.841540; Fri, 26 May 2023 11:07:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q2VIM-0007gR-TW; Fri, 26 May 2023 11:07:42 +0000 Received: by outflank-mailman (input) for mailman id 540061; Fri, 26 May 2023 11:07:40 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q2VIJ-0006sm-Tl for xen-devel@lists.xenproject.org; Fri, 26 May 2023 11:07:39 +0000 Received: from esa5.hc3370-68.iphmx.com (esa5.hc3370-68.iphmx.com [216.71.155.168]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 84d6f7e6-fbb5-11ed-b230-6b7b168915f2; Fri, 26 May 2023 13:07:37 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 84d6f7e6-fbb5-11ed-b230-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1685099257; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tRC3UNaCj65Aajc92g1f04RU5FXAg5eRZ78lBWu320s=; b=LM1gi+wmkEVqhGjUQ7uNSs8gDNE+T9yfECPD10vO/zN6lcPbZhf9wxJ0 ArK/L+GdX8fwxvzLj6ZVNRqGGxeBvFd1vKjk5CG/KB+f8YliAIaGbqb0S Z05gtVJakFiqbVsZ90PJP8/dsciMpTDEr2omoWG9VdRFFQxNcqsBaKYRr U=; Authentication-Results: esa5.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none X-SBRS: 4.0 X-MesageID: 109294592 X-Ironport-Server: esa5.hc3370-68.iphmx.com X-Remote-IP: 162.221.156.123 X-Policy: $RELAYED IronPort-Data: A9a23:cBW1faP5CyulEM/vrR21l8FynXyQoLVcMsEvi/4bfWQNrUpz0jAFz WMcXjiDPfeJMGL9ft4nb460oUgF78PTmtZgQQto+SlhQUwRpJueD7x1DKtS0wC6dZSfER09v 63yTvGacajYm1eF/k/F3oDJ9CU6jufQAOKnUoYoAwgpLSd8UiAtlBl/rOAwh49skLCRDhiE/ Nj/uKUzAnf8s9JPGjxSs/rrRC9H5qyo42tF5AJmP5ingXeF/5UrJMNHTU2OByOQrrl8RoaSW +vFxbelyWLVlz9F5gSNy+uTnuUiG9Y+DCDW4pZkc/HKbitq/0Te5p0TJvsEAXq7vh3S9zxHJ HehgrTrIeshFvWkdO3wyHC0GQkmVUFN0OevzXRSLaV/ZqAJGpfh66wGMa04AWEX0s14WE9x9 60pESgENkGDpP2Q3r38Q/Y506zPLOGzVG8eknRpzDWfBvc6W5HTBa7N4Le03h9p2JoIR6yHI ZNEN3w2Nk+ojx5nYz/7DLoXmuuyi2a5WDpfsF+P/oI84nTJzRw327/oWDbQUoXSFJ8EwhvJ/ Aoq+UynLT0YHvKalwOOzViV3umegTvSCawdQejQGvlC3wTImz175ActfUS/iem0jAi5Qd03A 1wZ/G8ioLY/8GSvT8LhRFuorXicpBkeVtFMVeog52ml6IDZ/gKYDWgsVSNaZZots8peeNAx/ gbXxZWzX2Up6eDLDyvHrd94sA9eJwA+IjYsWi1VfDId6oGyoKIsqAzACd98RfvdYsLOJRn8x DWDrS4bjroVjNIW26jTwW0rkw5AtbCSEFdru1y/snaNq1ogOdX7P9DABU3zt64oEWqPcrWWU JHoceC65ftGM5yCnTflrA4lTODwvKbt3NExbDdS83gdG9aFoSbLkWN4umsWyKJV3iEsJ1fUj Lf741852XOqFCLCgVVLS4ywEd826qPrCM7oUPvZBvIXPMgsLFTWoH03Ox/Kt4wIrKTKuftjU Xt8WZ/2ZUv29Iw9lGbmLwvj+eNDKt8CKZP7GsmgkkXPPUu2b3+JU7YVWGazghQCxPrc+m39q o8PX/ZmPj0DCIUSlAGLq99MRb3LRFBnba3LRzt/LLPbeVY+QzhwUpc8A9oJIuRYokicrc+Ql lnVZ6OS4Aak7ZEbAW1mskxeVY4= IronPort-HdrOrdr: A9a23:VFnX+K3Pp0nw9MLWDklb9wqjBEIkLtp133Aq2lEZdPU0SKGlfq GV7ZAmPHrP4gr5N0tOpTntAse9qBDnhPtICOsqTNSftWDd0QPFEGgF1+rfKlXbcBEWndQtt5 uIHZIfNDSKNykcsS77ijPIb+rJwrO8gd+VbTG19QYSceloAZsQnjuQEmygYytLrJEtP+tCKH KbjPA33gaISDAsQemQIGIKZOTHr82jruOaXfZXbyRXkDVnlFmTmcXHLyQ= X-Talos-CUID: 9a23:nFnHrmkr7iIBbMER6dP25rr6IULXOVbSlVnvIR6JMH5gEOyVakC25qwjmtU7zg== X-Talos-MUID: 9a23:jwmPlgkPzsQImLdwUzX6dno8G+tqyYqrVnkGrr8/48/VKTRZahmS2WE= X-IronPort-AV: E=Sophos;i="6.00,194,1681185600"; d="scan'208";a="109294592" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH 1/4] x86/spec-ctrl: Rename retpoline_safe() to retpoline_calculations() Date: Fri, 26 May 2023 12:06:52 +0100 Message-ID: <20230526110656.4018711-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230526110656.4018711-1-andrew.cooper3@citrix.com> References: <20230526110656.4018711-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 This is prep work, split out to simply the diff on the following change. * Rename to retpoline_calculations(), and call unconditionally. It is shortly going to synthesize missing enumerations required for guest safety. * For Broadwell, store the ucode revision calculation in a variable and fall out of the bottom of the switch statement. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné CC: Wei Liu --- xen/arch/x86/spec_ctrl.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 50d467f74cf8..0774d40627dd 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -579,9 +579,10 @@ static bool __init check_smt_enabled(void) } /* Calculate whether Retpoline is known-safe on this CPU. */ -static bool __init retpoline_safe(void) +static bool __init retpoline_calculations(void) { unsigned int ucode_rev = this_cpu(cpu_sig).rev; + bool safe = false; if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) return true; @@ -626,18 +627,18 @@ static bool __init retpoline_safe(void) * versions. */ case 0x3d: /* Broadwell */ - return ucode_rev >= 0x2a; + safe = ucode_rev >= 0x2a; break; case 0x47: /* Broadwell H */ - return ucode_rev >= 0x1d; + safe = ucode_rev >= 0x1d; break; case 0x4f: /* Broadwell EP/EX */ - return ucode_rev >= 0xb000021; + safe = ucode_rev >= 0xb000021; break; case 0x56: /* Broadwell D */ switch ( boot_cpu_data.x86_mask ) { - case 2: return ucode_rev >= 0x15; - case 3: return ucode_rev >= 0x7000012; - case 4: return ucode_rev >= 0xf000011; - case 5: return ucode_rev >= 0xe000009; + case 2: safe = ucode_rev >= 0x15; break; + case 3: safe = ucode_rev >= 0x7000012; break; + case 4: safe = ucode_rev >= 0xf000011; break; + case 5: safe = ucode_rev >= 0xe000009; break; default: printk("Unrecognised CPU stepping %#x - assuming not reptpoline safe\n", boot_cpu_data.x86_mask); @@ -681,6 +682,12 @@ static bool __init retpoline_safe(void) boot_cpu_data.x86_model); return false; } + + /* Only Broadwell gets here. */ + if ( safe ) + return true; + + return false; } /* @@ -1113,7 +1120,7 @@ void __init init_speculation_mitigations(void) { enum ind_thunk thunk = THUNK_DEFAULT; bool has_spec_ctrl, ibrs = false, hw_smt_enabled; - bool cpu_has_bug_taa; + bool cpu_has_bug_taa, retpoline_safe; hw_smt_enabled = check_smt_enabled(); @@ -1139,6 +1146,9 @@ void __init init_speculation_mitigations(void) thunk = THUNK_JMP; } + /* Determine if retpoline is safe on this CPU. */ + retpoline_safe = retpoline_calculations(); + /* * Has the user specified any custom BTI mitigations? If so, follow their * instructions exactly and disable all heuristics. @@ -1160,7 +1170,7 @@ void __init init_speculation_mitigations(void) * On all hardware, we'd like to use retpoline in preference to * IBRS, but only if it is safe on this hardware. */ - if ( retpoline_safe() ) + if ( retpoline_safe ) thunk = THUNK_RETPOLINE; else if ( has_spec_ctrl ) ibrs = true;