diff mbox series

[v8,12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm

Message ID 20230531072413.868673-13-luca.fancellu@arm.com (mailing list archive)
State Accepted
Headers show
Series SVE feature for arm guests | expand

Commit Message

Luca Fancellu May 31, 2023, 7:24 a.m. UTC 
Arm now can use the "dom0=" Xen command line option and the support
for guests running SVE instructions is added, put entries in the
changelog.

Mention the "Tech Preview" status and add an entry in SUPPORT.md

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: Henry Wang <Henry.Wang@arm.com> # CHANGELOG
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
Changes from v7:
 - Add r-by Bertrand
 - Use 'Arm64 domains' instead of 'AArch64 guest' in SUPPORT.md
   (Julien)
Changes from v6:
 - Add Henry's A-by to CHANGELOG
Changes from v5:
 - Add Tech Preview status and add entry in SUPPORT.md (Bertrand)
Changes from v4:
 - No changes
Change from v3:
 - new patch
---
 CHANGELOG.md | 3 +++
 SUPPORT.md   | 6 ++++++
 2 files changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5bfd3aa5c0d5..512b7bdc0fcb 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -11,6 +11,8 @@  The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    cap toolstack provided values.
  - Ignore VCPUOP_set_singleshot_timer's VCPU_SSHOTTMR_future flag. The only
    known user doesn't use it properly, leading to in-guest breakage.
+ - The "dom0" option is now supported on Arm and "sve=" sub-option can be used
+   to enable dom0 guest to use SVE/SVE2 instructions.
 
 ### Added
  - On x86, support for features new in Intel Sapphire Rapids CPUs:
@@ -20,6 +22,7 @@  The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - Bus-lock detection, used by Xen to mitigate (by rate-limiting) the system
      wide impact of a guest misusing atomic instructions.
  - xl/libxl can customize SMBIOS strings for HVM guests.
+ - On Arm, Xen supports guests running SVE/SVE2 instructions. (Tech Preview)
 
 ## [4.17.0](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.17.0) - 2022-12-12
 
diff --git a/SUPPORT.md b/SUPPORT.md
index 6dbed9d5d029..c0aeb1f3f5e0 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -99,6 +99,12 @@  Extension to the GICv3 interrupt controller to support MSI.
 
     Status: Experimental
 
+### ARM Scalable Vector Extension (SVE/SVE2)
+
+Arm64 domains can use Scalable Vector Extension (SVE/SVE2).
+
+    Status: Tech Preview
+
 ## Guest Type
 
 ### x86/PV