From patchwork Wed May 31 07:24:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13261569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E0C1C77B73 for ; Wed, 31 May 2023 07:24:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.541563.844537 (Exim 4.92) (envelope-from ) id 1q4GCK-0008Vi-TD; Wed, 31 May 2023 07:24:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 541563.844537; Wed, 31 May 2023 07:24:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q4GCK-0008UI-FA; Wed, 31 May 2023 07:24:44 +0000 Received: by outflank-mailman (input) for mailman id 541563; Wed, 31 May 2023 07:24:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q4GCI-0005os-Oz for xen-devel@lists.xenproject.org; Wed, 31 May 2023 07:24:42 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id 34ed7b53-ff84-11ed-8611-37d641c3527e; Wed, 31 May 2023 09:24:40 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3965D1063; Wed, 31 May 2023 00:25:26 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 71CC43F663; Wed, 31 May 2023 00:24:39 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 34ed7b53-ff84-11ed-8611-37d641c3527e From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: bertrand.marquis@arm.com, wei.chen@arm.com, Henry Wang , Community Manager , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v8 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm Date: Wed, 31 May 2023 08:24:13 +0100 Message-Id: <20230531072413.868673-13-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531072413.868673-1-luca.fancellu@arm.com> References: <20230531072413.868673-1-luca.fancellu@arm.com> MIME-Version: 1.0 Arm now can use the "dom0=" Xen command line option and the support for guests running SVE instructions is added, put entries in the changelog. Mention the "Tech Preview" status and add an entry in SUPPORT.md Signed-off-by: Luca Fancellu Acked-by: Henry Wang # CHANGELOG Reviewed-by: Bertrand Marquis --- Changes from v7: - Add r-by Bertrand - Use 'Arm64 domains' instead of 'AArch64 guest' in SUPPORT.md (Julien) Changes from v6: - Add Henry's A-by to CHANGELOG Changes from v5: - Add Tech Preview status and add entry in SUPPORT.md (Bertrand) Changes from v4: - No changes Change from v3: - new patch --- CHANGELOG.md | 3 +++ SUPPORT.md | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5bfd3aa5c0d5..512b7bdc0fcb 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) cap toolstack provided values. - Ignore VCPUOP_set_singleshot_timer's VCPU_SSHOTTMR_future flag. The only known user doesn't use it properly, leading to in-guest breakage. + - The "dom0" option is now supported on Arm and "sve=" sub-option can be used + to enable dom0 guest to use SVE/SVE2 instructions. ### Added - On x86, support for features new in Intel Sapphire Rapids CPUs: @@ -20,6 +22,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - Bus-lock detection, used by Xen to mitigate (by rate-limiting) the system wide impact of a guest misusing atomic instructions. - xl/libxl can customize SMBIOS strings for HVM guests. + - On Arm, Xen supports guests running SVE/SVE2 instructions. (Tech Preview) ## [4.17.0](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.17.0) - 2022-12-12 diff --git a/SUPPORT.md b/SUPPORT.md index 6dbed9d5d029..c0aeb1f3f5e0 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -99,6 +99,12 @@ Extension to the GICv3 interrupt controller to support MSI. Status: Experimental +### ARM Scalable Vector Extension (SVE/SVE2) + +Arm64 domains can use Scalable Vector Extension (SVE/SVE2). + + Status: Tech Preview + ## Guest Type ### x86/PV