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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id b3-20020a5d4d83000000b0030c4d8930b1sm10247405wru.91.2023.06.05.10.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 10:08:22 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 93f918b1-03c3-11ee-b232-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1685984902; x=1688576902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B7fxp0WbBbMKypEvumAuysCY0BLPaaSmYzs2KisIH00=; b=bX0ieJYw9ilCPO+NbFfqK7wmgNzrSz8WqwisW2uzz/F58LwomsoRUNxVU/i/WGqfaQ lZDdLqJq6dZF10AgGibJjPShDGdlH5pAKtuVCSzQwzB0WMfobdEzZrNvvqejBeWbzWVN aQjOl1ZJpdzNSM+ARk8icJpA5JN6s04TimjUU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685984902; x=1688576902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B7fxp0WbBbMKypEvumAuysCY0BLPaaSmYzs2KisIH00=; b=HmV6YC1GXWatxpowOlgwWod4++AiJXc58twQGaN3lq37VYV9tHbgcltSODtAPea9Ym 8wvzPfhFhNmuw05JFrjZ5t2aQmyns1/5FWX4UTxST8PGfpV5cT7LRnBFEBBWCQ5npJ1u aIQUNMsN1wAjbBVcp7+qiDtaM57ztw4tzeEPJiXuoEsAdwwS/sECG63coJkeN144TzQf v4I1Z7EHlzXkdt63LRARYGaZOiQSm91UwwuW/fmWtW+XSppS8DfSPN/PwYG7iYHm1H+X pydjfkz7mMEivqk7SpK8/KbCKa3BWdHINOGxubKGbDMKjkMhm3ZFNaS61L09zngzt/xO SpvA== X-Gm-Message-State: AC+VfDwrB05YE1ubZAHJAAPBzkcfsJ5l9bn2WSW4CbRfQbp6WmYh1QlG LxVk2NozCg/on8TNVmsN0dOiSHihA1ru29/36Wo= X-Google-Smtp-Source: ACHHUZ6yjFhHjZcRl5U8qb7QH1Jqd7Os8ifx204lVxQq/+5cXpNuDf1O+km9wHvsj/hChpQ2U9HCYw== X-Received: by 2002:a05:6000:44:b0:306:4162:ebbe with SMTP id k4-20020a056000004400b003064162ebbemr6411420wrx.49.1685984902557; Mon, 05 Jun 2023 10:08:22 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 2/4] x86: Read MSR_ARCH_CAPS after early_microcode_init() Date: Mon, 5 Jun 2023 18:08:15 +0100 Message-Id: <20230605170817.9913-3-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605170817.9913-1-alejandro.vallejo@cloud.com> References: <20230605170817.9913-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 tsx_init() has some ad-hoc code to read MSR_ARCH_CAPS if present. In order to suuport DIS_MCU_UPDATE we need access to it earlier, so this patch moves early read to the tail of early_microcode_init(), after the early microcode update. The read of the 7d0 CPUID leaf is left in a helper because it's reused in a later patch. No functional change. Signed-off-by: Alejandro Vallejo --- I suspect there was an oversight in tsx_init() by which boot_cpu_data.cpuid_level was never read? The first read I can see is in identify_cpu(), which happens after tsx_init(). v2: * New addition --- xen/arch/x86/cpu/microcode/core.c | 21 +++++++++++++++++++++ xen/arch/x86/tsx.c | 15 +++------------ 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 29ff38f35c..892bcec901 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -840,6 +840,15 @@ static int __init early_microcode_update_cpu(void) return microcode_update_cpu(patch); } +static void __init early_read_cpuid_7d0(void) +{ + boot_cpu_data.cpuid_level = cpuid_eax(0); + + if ( boot_cpu_data.cpuid_level >= 7 ) + boot_cpu_data.x86_capability[FEATURESET_7d0] + = cpuid_count_edx(7, 0); +} + int __init early_microcode_init(unsigned long *module_map, const struct multiboot_info *mbi) { @@ -878,5 +887,17 @@ int __init early_microcode_init(unsigned long *module_map, if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); + early_read_cpuid_7d0(); + + /* + * tsx_init() needs MSR_ARCH_CAPS, but it runs before identify_cpu() + * populates boot_cpu_data, so we read it here to centralize early + * CPUID/MSR reads in the same place. + */ + if ( cpu_has_arch_caps ) + rdmsr(MSR_ARCH_CAPABILITIES, + boot_cpu_data.x86_capability[FEATURESET_m10Al], + boot_cpu_data.x86_capability[FEATURESET_m10Ah]); + return rc; } diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 80c6f4cedd..0501e181bf 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -39,9 +39,9 @@ void tsx_init(void) static bool __read_mostly once; /* - * This function is first called between microcode being loaded, and CPUID - * being scanned generally. Read into boot_cpu_data.x86_capability[] for - * the cpu_has_* bits we care about using here. + * While MSRs/CPUID haven't yet been scanned, MSR_ARCH_CAPABILITIES + * and leaf 7d0 have already been read if present after early microcode + * loading time. So we can assume _those_ are present. */ if ( unlikely(!once) ) { @@ -49,15 +49,6 @@ void tsx_init(void) once = true; - if ( boot_cpu_data.cpuid_level >= 7 ) - boot_cpu_data.x86_capability[FEATURESET_7d0] - = cpuid_count_edx(7, 0); - - if ( cpu_has_arch_caps ) - rdmsr(MSR_ARCH_CAPABILITIES, - boot_cpu_data.x86_capability[FEATURESET_m10Al], - boot_cpu_data.x86_capability[FEATURESET_m10Ah]); - has_rtm_always_abort = cpu_has_rtm_always_abort; if ( cpu_has_tsx_ctrl && cpu_has_srbds_ctrl )