@@ -13,7 +13,8 @@
#include <asm/msr.h>
#include <acpi/cpufreq/cpufreq.h>
-static bool __ro_after_init feature_hwp;
+static bool __ro_after_init hwp_in_use;
+
static bool __ro_after_init feature_hwp_notification;
static bool __ro_after_init feature_hwp_activity_window;
@@ -168,6 +169,11 @@ static int __init cf_check cpufreq_gov_hwp_init(void)
}
__initcall(cpufreq_gov_hwp_init);
+bool hwp_active(void)
+{
+ return hwp_in_use;
+}
+
bool __init hwp_available(void)
{
unsigned int eax;
@@ -211,7 +217,6 @@ bool __init hwp_available(void)
return false;
}
- feature_hwp = eax & CPUID6_EAX_HWP;
feature_hwp_notification = eax & CPUID6_EAX_HWP_NOTIFICATION;
feature_hwp_activity_window = eax & CPUID6_EAX_HWP_ACTIVITY_WINDOW;
feature_hdc = eax & CPUID6_EAX_HDC;
@@ -224,12 +229,13 @@ bool __init hwp_available(void)
hwp_verbose("HW_FEEDBACK %ssupported\n",
(eax & CPUID6_EAX_HW_FEEDBACK) ? "" : "not ");
- cpufreq_governor_internal = feature_hwp;
+ hwp_in_use = eax & CPUID6_EAX_HWP;
+ cpufreq_governor_internal = hwp_in_use;
- if ( feature_hwp )
+ if ( hwp_in_use )
hwp_info("Using HWP for cpufreq\n");
- return feature_hwp;
+ return hwp_in_use;
}
static int hdc_set_pkg_hdc_ctl(unsigned int cpu, bool val)
@@ -26,6 +26,8 @@
#include <asm/fixmap.h>
#include <asm/mwait.h>
+#include <acpi/cpufreq/processor_perf.h>
+
u32 __read_mostly acpi_smi_cmd;
u8 __read_mostly acpi_enable_value;
u8 __read_mostly acpi_disable_value;
@@ -140,5 +142,8 @@ int arch_acpi_set_pdc_bits(u32 acpi_id, u32 *pdc, u32 mask)
!(ecx & CPUID5_ECX_INTERRUPT_BREAK))
pdc[2] &= ~(ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH);
+ if (hwp_active())
+ pdc[2] |= ACPI_PDC_CPPC_NATIVE_INTR;
+
return 0;
}
@@ -15,6 +15,9 @@
#include <asm/p2m.h>
#include <asm/mce.h>
#include <asm/apic.h>
+
+#include <acpi/cpufreq/processor_perf.h>
+
#include "mce.h"
#include "x86_mca.h"
#include "barrier.h"
@@ -64,6 +67,9 @@ static void cf_check intel_thermal_interrupt(struct cpu_user_regs *regs)
ack_APIC_irq();
+ if ( hwp_active() )
+ wrmsr_safe(MSR_HWP_STATUS, 0);
+
if ( NOW() < per_cpu(next, cpu) )
return;
@@ -157,6 +157,7 @@
#define MSR_HWP_CAPABILITIES 0x00000771
#define MSR_HWP_INTERRUPT 0x00000773
#define MSR_HWP_REQUEST 0x00000774
+#define MSR_HWP_STATUS 0x00000777
#define MSR_X2APIC_FIRST 0x00000800
#define MSR_X2APIC_LAST 0x000008ff
@@ -8,6 +8,7 @@
#define XEN_PX_INIT 0x80000000
bool hwp_available(void);
+bool hwp_active(void);
int hwp_register_driver(void);
int powernow_cpufreq_init(void);
@@ -17,6 +17,7 @@
#define ACPI_PDC_C_C1_FFH (0x0100)
#define ACPI_PDC_C_C2C3_FFH (0x0200)
#define ACPI_PDC_SMP_P_HWCOORD (0x0800)
+#define ACPI_PDC_CPPC_NATIVE_INTR (0x1000)
#define ACPI_PDC_EST_CAPABILITY_SMP (ACPI_PDC_SMP_C1PT | \
ACPI_PDC_C_C1_HALT | \