From patchwork Mon Jun 19 17:01:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13284840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFD2FEB64DA for ; Mon, 19 Jun 2023 17:01:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551244.860700 (Exim 4.92) (envelope-from ) id 1qBIFo-0003vI-UP; Mon, 19 Jun 2023 17:01:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551244.860700; Mon, 19 Jun 2023 17:01:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFo-0003v5-RT; Mon, 19 Jun 2023 17:01:24 +0000 Received: by outflank-mailman (input) for mailman id 551244; Mon, 19 Jun 2023 17:01:23 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFn-0003a0-1I for xen-devel@lists.xenproject.org; Mon, 19 Jun 2023 17:01:23 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFm-0002eQ-Qi; Mon, 19 Jun 2023 17:01:22 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qBIFm-00079R-J2; Mon, 19 Jun 2023 17:01:22 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=AZgk+a7RNDOh2A2w6FC7dZLd0kw2EJlcWOaKZ6/xmw4=; b=oWFRU/Nui2FPz+c6D8HfjYv9kE 7UJr+ZMGk3FwaAhChv7+Jq/tFDBMGBl2OcdiB8lxzE9UJCT6/oUAksDrG7MNcwjJH6+ln8uRXwIjt i6zkzSAJOyqElzd0VyznmD9T3w5n3F2zG3yIUDgh2XSR7nj0cbOitDGgT4u8bXa5WEqI=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/7] xen/arm64: head: Add missing isb in setup_fixmap() Date: Mon, 19 Jun 2023 18:01:11 +0100 Message-Id: <20230619170115.81398-4-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619170115.81398-1-julien@xen.org> References: <20230619170115.81398-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall On older version of the Arm Arm (ARM DDI 0487E.a, B2-125) there were the following paragraph: "DMB and DSB instructions affect reads and writes to the memory system generated by Load/Store instructions and data or unified cache maintenance instructions being executed by the PE. Instruction fetches or accesses caused by a hardware translation table access are not explicit accesses." Newer revision (e.g. ARM DDI 0487J.a) doesn't have the second sentence (it might be somewhere else in the Arm Arm). But the interpretation is not much different. In setup_fixmap(), we write the fixmap area and may be used soon after, for instance, to write to the UART. IOW, there could be hardware translation table access. So we need to ensure the 'dsb' has completed before continuing. Therefore add an 'isb'. Fixes: 2b11c3646105 ("xen/arm64: head: Remove 1:1 mapping as soon as it is not used") Signed-off-by: Julien Grall Reviewed-by: Henry Wang Tested-by: Henry Wang Reviewed-by: Luca Fancellu Reviewed-by: Michal Orzel Reviewed-by: Bertrand Marquis --- xen/arch/arm/arm64/head.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index f37133cf7ccd..4ea64e70997b 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -769,6 +769,11 @@ setup_fixmap: create_table_entry boot_second, xen_fixmap, x0, 2, x1, x2, x3 /* Ensure any page table updates made above have occurred. */ dsb nshst + /* + * The fixmap area will be used soon after. So ensure no hardware + * translation happens before the dsb completes. + */ + isb ret ENDPROC(setup_fixmap)