@@ -12,6 +12,8 @@
#include <asm/msr.h>
#include <acpi/cpufreq/cpufreq.h>
+static bool __ro_after_init hwp_in_use;
+
static bool __ro_after_init feature_hwp_notification;
static bool __ro_after_init feature_hwp_activity_window;
@@ -152,6 +154,11 @@ static int __init cf_check cpufreq_gov_hwp_init(void)
}
__initcall(cpufreq_gov_hwp_init);
+bool hwp_active(void)
+{
+ return hwp_in_use;
+}
+
static bool __init hwp_available(void)
{
unsigned int eax;
@@ -204,6 +211,8 @@ static bool __init hwp_available(void)
hwp_verbose("HW_FEEDBACK %ssupported\n",
(eax & CPUID6_EAX_HW_FEEDBACK) ? "" : "not ");
+ hwp_in_use = true;
+
hwp_info("Using HWP for cpufreq\n");
return true;
@@ -26,6 +26,8 @@
#include <asm/fixmap.h>
#include <asm/mwait.h>
+#include <acpi/cpufreq/cpufreq.h>
+
u32 __read_mostly acpi_smi_cmd;
u8 __read_mostly acpi_enable_value;
u8 __read_mostly acpi_disable_value;
@@ -140,5 +142,8 @@ int arch_acpi_set_pdc_bits(u32 acpi_id, u32 *pdc, u32 mask)
!(ecx & CPUID5_ECX_INTERRUPT_BREAK))
pdc[2] &= ~(ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH);
+ if (hwp_active())
+ pdc[2] |= ACPI_PDC_CPPC_NATIVE_INTR;
+
return 0;
}
@@ -15,6 +15,9 @@
#include <asm/p2m.h>
#include <asm/mce.h>
#include <asm/apic.h>
+
+#include <acpi/cpufreq/cpufreq.h>
+
#include "mce.h"
#include "x86_mca.h"
#include "barrier.h"
@@ -64,6 +67,9 @@ static void cf_check intel_thermal_interrupt(struct cpu_user_regs *regs)
ack_APIC_irq();
+ if ( hwp_active() )
+ wrmsr_safe(MSR_HWP_STATUS, 0);
+
if ( NOW() < per_cpu(next, cpu) )
return;
@@ -157,6 +157,7 @@
#define MSR_HWP_CAPABILITIES 0x00000771
#define MSR_HWP_INTERRUPT 0x00000773
#define MSR_HWP_REQUEST 0x00000774
+#define MSR_HWP_STATUS 0x00000777
#define MSR_X2APIC_FIRST 0x00000800
#define MSR_X2APIC_LAST 0x000008ff
@@ -254,5 +254,6 @@ void intel_feature_detect(struct cpufreq_policy *policy);
int hwp_cmdline_parse(const char *s, const char *e);
int hwp_register_driver(void);
+bool hwp_active(void);
#endif /* __XEN_CPUFREQ_PM_H__ */
@@ -17,6 +17,7 @@
#define ACPI_PDC_C_C1_FFH (0x0100)
#define ACPI_PDC_C_C2C3_FFH (0x0200)
#define ACPI_PDC_SMP_P_HWCOORD (0x0800)
+#define ACPI_PDC_CPPC_NATIVE_INTR (0x1000)
#define ACPI_PDC_EST_CAPABILITY_SMP (ACPI_PDC_SMP_C1PT | \
ACPI_PDC_C_C1_HALT | \
Qubes testing of HWP support had a report of a laptop, Thinkpad X1 Carbon Gen 4 with a Skylake processor, locking up during boot when HWP is enabled. A user found a kernel bug that seems to be the same issue: https://bugzilla.kernel.org/show_bug.cgi?id=110941. That bug was fixed by Linux commit a21211672c9a ("ACPI / processor: Request native thermal interrupt handling via _OSC"). The tl;dr is SMM crashes when it receives thermal interrupts, so Linux calls the ACPI _OSC method to take over interrupt handling. The Linux fix looks at the CPU features to decide whether or not to call _OSC with bit 12 set to take over native interrupt handling. Xen needs some way to communicate HWP to Dom0 for making an equivalent call. Xen exposes modified PDC bits via the platform_op set_pminfo hypercall. Expand that to set bit 12 when HWP is present and in use. Any generated interrupt would be handled by Xen's thermal drive, which clears the status. Bit 12 isn't named in the linux header and is open coded in Linux's usage. Name it ACPI_PDC_CPPC_NATIVE_INTR. This will need a corresponding linux patch to pick up and apply the PDC bits. Signed-off-by: Jason Andryuk <jandryuk@gmail.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- v5: Minor fixup for feature_hwp removal Use cpurfreq.h for declaration v4: Added __ro_after_init s/ACPI_PDC_CPPC_NTV_INT/ACPI_PDC_CPPC_NATIVE_INTR/ Remove _IA32_ Fixup for opt_cpufreq_hwp removal Add Jan Reviewed-by v3: New --- xen/arch/x86/acpi/cpufreq/hwp.c | 9 +++++++++ xen/arch/x86/acpi/lib.c | 5 +++++ xen/arch/x86/cpu/mcheck/mce_intel.c | 6 ++++++ xen/arch/x86/include/asm/msr-index.h | 1 + xen/include/acpi/cpufreq/cpufreq.h | 1 + xen/include/acpi/pdc_intel.h | 1 + 6 files changed, 23 insertions(+)