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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu Subject: [PATCH v5 3/5] xen/pci: update PCI_STATUS_* constants Date: Fri, 1 Sep 2023 00:57:30 -0400 Message-ID: <20230901045742.235975-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230901045742.235975-1-stewart.hildebrand@amd.com> References: <20230901045742.235975-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3A:EE_|MN2PR12MB4344:EE_ X-MS-Office365-Filtering-Correlation-Id: 8671c735-8bbf-46ae-0024-08dbaaa851c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5tf0om0kWnVBHXxoscfu1/afuAUO7NgASO06LKNuf6UTwA7OMk3nAH+20dz2EW0ahk5sqS+wHblXGD45hRjx1JBe/9kjOSzemLFPG+G9zYoCxHnB9/vjWg2sM+0QsjSRbwpXuAGrVGYFaQvwosjAqNR5naBO3OsqZyWsPtyFQ9mMZAfwKfDMfPcTUR9xWDMN/mR0BMMAauSeepzY15YBP9UfCgGFsoRBMGA0uEXCNaiMQxo/YVF0/GELu0VPJJ1n1wFCpMMh09x059/JpuP8IG17cMhhB6MVwiVtL3GgKjoYu2EmVG6ReyY4ejE6Q6r7Sr+t4mAEh44DTGDe/ysDqfENFjf5dxPLITfkhCM+Dafz1pjmMfIf+JybDlVeiTxDSWw5D+CN7VLXLOPrRUYlEorELa6aNbhL1PGEfSqwtl5syrsJEi8cTvWMYz3+wdK53i3rLdUiUTGtKD8ryk9mz890GltyuOWyVD2Ox6nHhDhZ4z5pszgaG0+MSOeXOY9/NNEiYrPOuaU3ybRWeXcQv4ntBpch0cGaSPQSnulagBO7OPBtKXEkZQ+395jKmjbpgdQYcOOXVNd3KErwRd8h4ttnApVktlRzFW0FmXCQyX44J8IgNiRFwiFpolNOYdoGeRDp4R3W6EDn7psglAnRwU1HuUc1DJv9Y6Vn+6HM6jMJ6xbptjb/eWQrXrQA4vQvs1vYVcmqKVjSwHJDo+xFIc2hal1ZQxIl0mfpltlwd8f7g2LDaiZE/vCyLOGx4h8prhN/XkIl5D1/PgJ/SJYz0w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(136003)(39860400002)(346002)(82310400011)(451199024)(186009)(1800799009)(36840700001)(46966006)(40470700004)(6666004)(36860700001)(82740400003)(356005)(40480700001)(81166007)(478600001)(47076005)(54906003)(316002)(41300700001)(70206006)(70586007)(86362001)(40460700003)(2906002)(5660300002)(426003)(6916009)(36756003)(4744005)(336012)(2616005)(1076003)(44832011)(26005)(8676002)(8936002)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2023 05:00:10.5121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8671c735-8bbf-46ae-0024-08dbaaa851c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4344 Interrupt status introduced in PCI 2.3 Immediate readiness introduced in PCIe 4.0 Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- v4->v5: * new patch --- xen/include/xen/pci_regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index a90aff1712ba..84b18736a85d 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -50,6 +50,8 @@ #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ #define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ +#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */