| Message ID | 20230904091406.942-2-michal.orzel@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | xen: fixes for UBSAN findings with SMMUv3 enabled | expand |
Hi Michal, > On 4 Sep 2023, at 11:14, Michal Orzel <michal.orzel@amd.com> wrote: > > When running with SMMUv3 and UBSAN enabled, the following is printed: > > (XEN) UBSAN: Undefined behaviour in drivers/passthrough/arm/smmu-v3.c:297:12 > (XEN) left shift of 1 by 31 places cannot be represented in type 'int' > > This refers to shift in Q_OVERFLOW_FLAG that is missing 'U' suffix. > While there, also fix the same in GBPA_UPDATE. > > This should address MISRA Rule 7.2: > A "u" or "U" suffix shall be applied to all integer constants that > are represented in an unsigned type > > Signed-off-by: Michal Orzel <michal.orzel@amd.com> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com> Cheers Bertrand > --- > xen/drivers/passthrough/arm/smmu-v3.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h > index b381ad373845..05f6b1fb7e33 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.h > +++ b/xen/drivers/passthrough/arm/smmu-v3.h > @@ -87,7 +87,7 @@ > #define CR2_E2H (1 << 0) > > #define ARM_SMMU_GBPA 0x44 > -#define GBPA_UPDATE (1 << 31) > +#define GBPA_UPDATE (1U << 31) > #define GBPA_ABORT (1 << 20) > > #define ARM_SMMU_IRQ_CTRL 0x50 > @@ -159,7 +159,7 @@ > > #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) > #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) > -#define Q_OVERFLOW_FLAG (1 << 31) > +#define Q_OVERFLOW_FLAG (1U << 31) > #define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) > #define Q_ENT(q, p) ((q)->base + \ > Q_IDX(&((q)->llq), p) * \ > -- > 2.25.1 >
diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h index b381ad373845..05f6b1fb7e33 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -87,7 +87,7 @@ #define CR2_E2H (1 << 0) #define ARM_SMMU_GBPA 0x44 -#define GBPA_UPDATE (1 << 31) +#define GBPA_UPDATE (1U << 31) #define GBPA_ABORT (1 << 20) #define ARM_SMMU_IRQ_CTRL 0x50 @@ -159,7 +159,7 @@ #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) -#define Q_OVERFLOW_FLAG (1 << 31) +#define Q_OVERFLOW_FLAG (1U << 31) #define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) #define Q_ENT(q, p) ((q)->base + \ Q_IDX(&((q)->llq), p) * \
When running with SMMUv3 and UBSAN enabled, the following is printed: (XEN) UBSAN: Undefined behaviour in drivers/passthrough/arm/smmu-v3.c:297:12 (XEN) left shift of 1 by 31 places cannot be represented in type 'int' This refers to shift in Q_OVERFLOW_FLAG that is missing 'U' suffix. While there, also fix the same in GBPA_UPDATE. This should address MISRA Rule 7.2: A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type Signed-off-by: Michal Orzel <michal.orzel@amd.com> --- xen/drivers/passthrough/arm/smmu-v3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)