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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , Ayan Kumar Halder Subject: [XEN v1 2/4] xen/arm32: head.S: Introduce enable_{boot,secondary}_cpu_mm() Date: Mon, 11 Sep 2023 14:59:40 +0100 Message-ID: <20230911135942.791206-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230911135942.791206-1-ayan.kumar.halder@amd.com> References: <20230911135942.791206-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003444:EE_|DS0PR12MB7745:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f51f141-1b18-4824-fcef-08dbb2cf810b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VJiYg1RMJ5R92LU8zGcShPIcgq280RaOoltvaUXww0Ak2Xu0BAENkw0vBovfBcR4qUdEKyy5h34qDKYMKqCc1BdsuNk2olHB+eDO91oG545Oz9EPAdMEkV9CCEfOTOmMOxp1A1e0U7452flLMYQYmMCn7EoJMUpZQk+LoeIN08XA49dy3dQY5bYiqLCagH4irr06zHXrntufPSHaLUuCbIFQMtVcYWsfiGbuRRti39SBmbvFOB/rMF7ye+FyzeghkdAXZDkQlYjVQypyvI9NjnVdmRN4WHcanf0N4bWGZIzjdXNzb6ESpt9b9GYpq3pirSqIZE8sYwShluqzume6qKxhBJ67d/CO54jciP9OYr5FBdXysMX1rvg9IjPODF9MlrzKx97MlQBeQOnnk7qnKUai1Bte1brC5MxYZ/XnpxOkpP4sJw2bVNhelCcn9U+V9XuiSAI4KiwgBvMksAVH6hq0dL93OqLN+jeKMEn4FSg0GaT4tVzW0e/CLyZePYHMlf/z7uCFzxRzMF8AT8c7c30RhjAA4ZwsqyCpRi0zUvdUS+JB7ToDELodpu8oin/FwM0oz+WCOZhIAPmoQW7t4nKN+0A4JO+rM60+qzacpNxAvJjyeG26/r3/FERisWOByg1MNq2PiBacO9H6SOdbLq7gPk4y594vX4ExZlZFKCjjDSbu34iPi042zhZDqa66H/DGsyNJfou1WN++e7DO7SnOEiluWyJ4UmCoTC0+ScdHY2pA0jeXXaDRHL6Ou2Tge6Ds0l7aot7PGyB0XrabZ0Sr7Z8i1zcsBVBeZlx/YJ8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(376002)(396003)(346002)(186009)(1800799009)(451199024)(82310400011)(40470700004)(36840700001)(46966006)(5660300002)(316002)(6916009)(54906003)(70206006)(36756003)(70586007)(8936002)(4326008)(8676002)(41300700001)(40460700003)(36860700001)(2906002)(336012)(1076003)(47076005)(426003)(26005)(40480700001)(82740400003)(6666004)(356005)(81166007)(478600001)(103116003)(2616005)(86362001)(966005)(83380400001)(21314003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2023 14:00:49.5296 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f51f141-1b18-4824-fcef-08dbb2cf810b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003444.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7745 This is based on:- "[PATCH v6 01/13] xen/arm64: head.S: Introduce enable_{boot,secondary}_cpu_mm()" https://www.mail-archive.com/xen-devel@lists.xenproject.org/msg151918.html This is being done for Arm32 as MPU support will be added for Arm32 as well. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/arm32/head.S | 90 +++++++++++++++++++++++++++++---------- 1 file changed, 67 insertions(+), 23 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 057c44a5a2..c0c425eac6 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -201,13 +201,10 @@ past_zImage: bl check_cpu_mode bl cpu_init - bl create_page_tables + ldr lr, =primary_switched + b enable_boot_cpu_mm - /* Address in the runtime mapping to jump to after the MMU is enabled */ - mov_w lr, primary_switched - b enable_mmu primary_switched: - bl setup_fixmap #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ mov_w r11, EARLY_UART_VIRTUAL_ADDRESS @@ -249,27 +246,11 @@ GLOBAL(init_secondary) #endif bl check_cpu_mode bl cpu_init - bl create_page_tables - /* Address in the runtime mapping to jump to after the MMU is enabled */ mov_w lr, secondary_switched - b enable_mmu -secondary_switched: - /* - * Non-boot CPUs need to move on to the proper pagetables, which were - * setup in prepare_secondary_mm. - * - * XXX: This is not compliant with the Arm Arm. - */ - mov_w r4, init_ttbr /* VA of HTTBR value stashed by CPU 0 */ - ldrd r4, r5, [r4] /* Actual value */ - dsb - mcrr CP64(r4, r5, HTTBR) - dsb - isb - flush_xen_tlb_local r0 - pt_enforce_wxn r0 + b enable_secondary_cpu_mm +secondary_switched: #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ mov_w r11, EARLY_UART_VIRTUAL_ADDRESS @@ -692,6 +673,69 @@ ready_to_switch: mov pc, lr ENDPROC(switch_to_runtime_mapping) +/* + * Enable mm (turn on the data cache and the MMU) for secondary CPUs. + * The function will return to the virtual address provided in LR (e.g. the + * runtime mapping). + * + * Inputs: + * lr : Virtual address to return to. + * + * Clobbers r0 - r6 + */ +enable_secondary_cpu_mm: + mov r6, lr + bl create_page_tables + + mov_w lr, secondary_cpu_mmu_on + b enable_mmu +secondary_cpu_mmu_on: + /* + * Non-boot CPUs need to move on to the proper pagetables, which were + * setup in prepare_secondary_mm. + * + * XXX: This is not compliant with the Arm Arm. + */ + mov_w r4, init_ttbr /* VA of HTTBR value stashed by CPU 0 */ + ldrd r4, r5, [r4] /* Actual value */ + dsb + mcrr CP64(r4, r5, HTTBR) + dsb + isb + flush_xen_tlb_local r0 + pt_enforce_wxn r0 + mov lr, r6 + + /* Return to the virtual address requested by the caller. */ + mov pc, lr +ENDPROC(enable_secondary_cpu_mm) + +/* + * Enable mm (turn on the data cache and the MMU) for the boot CPU. + * The function will return to the virtual address provided in LR (e.g. the + * runtime mapping). + * + * Inputs: + * lr : Virtual address to return to. + * + * Clobbers r0 - r6 + */ +enable_boot_cpu_mm: + mov r6, lr + bl create_page_tables + + /* Address in the runtime mapping to jump to after the MMU is enabled */ + mov_w lr, boot_cpu_mmu_on + b enable_mmu +boot_cpu_mmu_on: + bl setup_fixmap + + mov lr, r6 + + /* Return to the virtual address requested by the caller. */ + mov pc, lr +ENDPROC(enable_boot_cpu_mm) + /* * Remove the 1:1 map from the page-tables. It is not easy to keep track * where the 1:1 map was mapped, so we will look for the top-level entry