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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Stefano Stabellini , Julien Grall , Rahul Singh , Bertrand Marquis Subject: [PATCH v5 4/9] iommu/arm: iommu_add_dt_pci_sideband_ids phantom handling Date: Wed, 4 Oct 2023 10:55:48 -0400 Message-ID: <20231004145604.1085358-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|SN7PR12MB7177:EE_ X-MS-Office365-Filtering-Correlation-Id: 27c3f554-bd33-4391-fa32-08dbc4ea37c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: C/isnkQFCaDQCT/VizsNjbMlPgYV1NL2X8PEPdkGog6WU4iWs0YZGDJIXJqRxNI/VxxcJB/jo1AqlOFMH7xkvGTcpVszRlEavHcBFlv39aTGMuwatAWiniY9gJos474+oPBU5JA98oKpHrI8f31GwzBUPtIlAHlx7J099+mou6fpewSB3ACdzh/iIGSC1V6tYNJHoLenPRk4vAA2WvOloBvN0R7U1tJlkG4fThHM58yEcuvLoZZ6eSWa1mPi4QAnuWbU/2arhUzBh4wnTwL9qMpEygfRhP0RnntVIYcWza3W3je7nvFDo723dRtHESPNs9F2L4ESxQP7Z9z+MdyId8dhaeRRWZvv6oDXBxtj4l900s6PqKuV7kYu1RfqaPc2wtMCE/VsEI1wEZzBxzehhfohkEXYiLueqne4UA8LAs/JnC78aSx3aKO8SAnwqMLgqOrKnWDc8kUy/3tG9oRFLR3aX6KrZYiZM26lyQE5fzAxfs0V5i560XqfWzQeiE8OOwz7Z83SySOQ8Y9ThUXRK4iygRq8PIjHuH1svW2RYROc676OKeU/inMNIHBaXtdDWYf05q8iWp75jh3mxKT304N1dVX28/F1oukJRqdMYaRhRN4JsT3uKo1ceC1FJ0PRiSiNthIpHQGz0RExxhBtyPS2CXUydhTN17j6gYm7Lh0fv0eRinslxxOHKMGiTIuM2WBts7+sMaC71EkyfIg9W8SscmwdcIaO5UdzcteRDCkC1rbStrBWgX7P1F4myZEWODLSZngSA3UW6WJtZ1t6vA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(376002)(136003)(396003)(230922051799003)(64100799003)(186009)(451199024)(82310400011)(1800799009)(46966006)(36840700001)(40470700004)(83380400001)(478600001)(6666004)(26005)(1076003)(356005)(2616005)(82740400003)(81166007)(966005)(36860700001)(426003)(336012)(47076005)(70586007)(70206006)(316002)(54906003)(8936002)(8676002)(4326008)(41300700001)(86362001)(40480700001)(5660300002)(2906002)(36756003)(6916009)(40460700003)(44832011)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:57:23.9807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27c3f554-bd33-4391-fa32-08dbc4ea37c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7177 Handle phantom functions in iommu_add_dt_pci_sideband_ids(). Each phantom function will have a unique requestor ID (RID)/BDF. On ARM, we need to map/translate the RID/BDF to an AXI stream ID for each phantom function according to the pci-iommu device tree mapping [1]. The RID/BDF -> AXI stream ID mapping in DT could allow phantom devices (i.e. devices with phantom functions) to use different AXI stream IDs based on the (phantom) function. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/pci/pci-iommu.txt Signed-off-by: Stewart Hildebrand --- v4->v5: * no change v3->v4: * s/iommu_dt_pci_map_id/dt_map_id/ v2->v3: * new patch title (was: iommu/arm: iommu_add_dt_pci_device phantom handling) * rework loop to reduce duplication * s/iommu_fwspec_free(pci_to_dev(pdev))/iommu_fwspec_free(dev)/ v1->v2: * new patch --- xen/drivers/passthrough/device_tree.c | 33 ++++++++++++++++----------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/xen/drivers/passthrough/device_tree.c b/xen/drivers/passthrough/device_tree.c index 5ee81132cb4d..6159777aa26f 100644 --- a/xen/drivers/passthrough/device_tree.c +++ b/xen/drivers/passthrough/device_tree.c @@ -169,6 +169,7 @@ int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev) struct device *dev = pci_to_dev(pdev); const struct dt_device_node *np; int rc; + unsigned int devfn = pdev->devfn; if ( !iommu_enabled ) return NO_IOMMU; @@ -183,21 +184,27 @@ int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev) if ( !np ) return -ENODEV; - /* - * According to the Documentation/devicetree/bindings/pci/pci-iommu.txt - * from Linux. - */ - rc = dt_map_id(np, PCI_BDF(pdev->bus, pdev->devfn), "iommu-map", - "iommu-map-mask", &iommu_spec.np, iommu_spec.args); - if ( rc ) - return (rc == -ENODEV) ? NO_IOMMU : rc; + do { + /* + * According to the Documentation/devicetree/bindings/pci/pci-iommu.txt + * from Linux. + */ + rc = dt_map_id(np, PCI_BDF(pdev->bus, devfn), "iommu-map", + "iommu-map-mask", &iommu_spec.np, iommu_spec.args); + if ( rc ) + return (rc == -ENODEV) ? NO_IOMMU : rc; - rc = iommu_dt_xlate(dev, &iommu_spec); - if ( rc < 0 ) - { - iommu_fwspec_free(dev); - return -EINVAL; + rc = iommu_dt_xlate(dev, &iommu_spec); + if ( rc < 0 ) + { + iommu_fwspec_free(dev); + return -EINVAL; + } + + devfn += pdev->phantom_stride; } + while ( (devfn != pdev->devfn) && + (PCI_SLOT(devfn) == PCI_SLOT(pdev->devfn)) ); return rc; }