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According to the Intel VT-d specification, an IOMMU might support multiple AGAW values. The AGAW value for each device is set in the device context entry, however there's a caveat related to the value the field supports depending on the translation type: "When the Translation-type (T) field indicates pass-through (010b) or guest-mode (100b or 101b), this field must be programmed to indicate the largest AGAW value supported by hardware." Of the translation types listed above Xen only uses pass-through (010b), and hence we need to make sure the context entry AGAW field is set appropriately, or else the IOMMU will report invalid context entry errors. To do so calculate the IOMMU supported page table levels based on the last bit set in the SAGAW field, instead of the first one. This also allows making use of the widest address width supported by the IOMMU, in case multiple AGAWs are supported. Note that 859d11b27912 claims to replace the open-coded find_first_set_bit(), but it's actually replacing an open coded implementation to find the last set bit. Fixes: 859d11b27912 ('VT-d: prune SAGAW recognition') Signed-off-by: Roger Pau Monné --- xen/drivers/passthrough/vtd/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index ceef7359e553..be60d7573dae 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1328,7 +1328,7 @@ int __init iommu_alloc(struct acpi_drhd_unit *drhd) /* Calculate number of pagetable levels: 3 or 4. */ sagaw = cap_sagaw(iommu->cap); if ( sagaw & 6 ) - agaw = find_first_set_bit(sagaw & 6); + agaw = fls(sagaw & 6) - 1; if ( !agaw ) { printk(XENLOG_ERR VTDPREFIX "IOMMU: unsupported sagaw %x\n", sagaw);