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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Stefano Stabellini , Julien Grall , Rahul Singh , Bertrand Marquis Subject: [PATCH v6 4/9] iommu/arm: iommu_add_dt_pci_sideband_ids phantom handling Date: Thu, 9 Nov 2023 13:27:07 -0500 Message-ID: <20231109182716.367119-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109182716.367119-1-stewart.hildebrand@amd.com> References: <20231109182716.367119-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|SA1PR12MB7104:EE_ X-MS-Office365-Filtering-Correlation-Id: cf97dd45-08d0-4d91-0e62-08dbe151c2de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PCXEJo7IE89J/BshUdmZd1hL5ykGapnpFl/nD9OWIu4OGKpeMKcgXMBI4WGHdUAROFqSMiOfR2gdxBkcwftumXGJ/6cIfmayhTL7iPhSySWKLg5rZCmY5cNyQ2in46mGQKu1RSXfqcPB0DvopoLwLRJ8iFFeDY+6MydFxD6yrTbIMq8/3kqQ/lDstg9CJkDVSWMpAN9oYg28c9eGq+YSMUcbqSK4zEBq/nsrMncTVqasWPkSum6cx6Gh+l4BgvNmfnUsL1pfTkJltFJ80n0wDvpxAM109uk2tlyjftIpdpWNnzCzJ1A3re2haLDlmJYprjoiWObRMQM+YzJIBMR9gKEqYCcopLhVeR6jdTsBLKmo3+pcXZ8v3XHTzliogD8Hqc5aB7MCAF5TAbfQBD0b9vPv+SvslteIVvpkU9w5UuoPP0tMUfPfIsWwPAgdI9c1YXl9TUdnemMiB7w/6OKBJdvmyi58HR/42C7PJp6zjYTiseLwTen90n5hufGrfJai2Xj8El1qKKcM9pTHZsvPsT964ytsG7cx4d/qzg2znEo7ScXmkZyR15GIeYf02gLm/HsUaDlX3Lpno5sYPK2d4OwQVmfVVBCft95bdJebwHh4YTktR3Ir79+io6pKnQWuW0edeguHza83A8k+z3ZsJRQMzw6QUg409lLtkU557bFg30DoNahP6DN4M3jRAGCSwNZFcDUR87i5F7gGb4SrXFHvv7UPbpjZCeSGdslT0T960iScWjrtGpaDp8jhw1jxMoKJ4GDYovpwGr0m/Tv6wg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(346002)(376002)(396003)(230922051799003)(1800799009)(82310400011)(186009)(64100799003)(451199024)(40470700004)(46966006)(36840700001)(47076005)(44832011)(41300700001)(2616005)(478600001)(966005)(8676002)(26005)(336012)(4326008)(316002)(8936002)(5660300002)(83380400001)(36860700001)(70586007)(54906003)(70206006)(1076003)(6916009)(356005)(426003)(81166007)(2906002)(86362001)(82740400003)(40480700001)(36756003)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2023 18:29:08.0365 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf97dd45-08d0-4d91-0e62-08dbe151c2de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7104 Handle phantom functions in iommu_add_dt_pci_sideband_ids(). Each phantom function will have a unique requestor ID (RID)/BDF. On ARM, we need to map/translate the RID/BDF to an AXI stream ID for each phantom function according to the pci-iommu device tree mapping [1]. The RID/BDF -> AXI stream ID mapping in DT could allow phantom devices (i.e. devices with phantom functions) to use different AXI stream IDs based on the (phantom) function. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/pci/pci-iommu.txt Signed-off-by: Stewart Hildebrand --- v5->v6: * no change v4->v5: * no change v3->v4: * s/iommu_dt_pci_map_id/dt_map_id/ v2->v3: * new patch title (was: iommu/arm: iommu_add_dt_pci_device phantom handling) * rework loop to reduce duplication * s/iommu_fwspec_free(pci_to_dev(pdev))/iommu_fwspec_free(dev)/ v1->v2: * new patch --- xen/drivers/passthrough/device_tree.c | 33 ++++++++++++++++----------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/xen/drivers/passthrough/device_tree.c b/xen/drivers/passthrough/device_tree.c index edbd3f17adc5..eba1a5bac70a 100644 --- a/xen/drivers/passthrough/device_tree.c +++ b/xen/drivers/passthrough/device_tree.c @@ -169,6 +169,7 @@ int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev) struct device *dev = pci_to_dev(pdev); const struct dt_device_node *np; int rc; + unsigned int devfn = pdev->devfn; if ( !iommu_enabled ) return NO_IOMMU; @@ -183,21 +184,27 @@ int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev) if ( !np ) return -ENODEV; - /* - * According to the Documentation/devicetree/bindings/pci/pci-iommu.txt - * from Linux. - */ - rc = dt_map_id(np, PCI_BDF(pdev->bus, pdev->devfn), "iommu-map", - "iommu-map-mask", &iommu_spec.np, iommu_spec.args); - if ( rc ) - return (rc == -ENODEV) ? NO_IOMMU : rc; + do { + /* + * According to the Documentation/devicetree/bindings/pci/pci-iommu.txt + * from Linux. + */ + rc = dt_map_id(np, PCI_BDF(pdev->bus, devfn), "iommu-map", + "iommu-map-mask", &iommu_spec.np, iommu_spec.args); + if ( rc ) + return (rc == -ENODEV) ? NO_IOMMU : rc; - rc = iommu_dt_xlate(dev, &iommu_spec, ops); - if ( rc < 0 ) - { - iommu_fwspec_free(dev); - return -EINVAL; + rc = iommu_dt_xlate(dev, &iommu_spec, ops); + if ( rc < 0 ) + { + iommu_fwspec_free(dev); + return -EINVAL; + } + + devfn += pdev->phantom_stride; } + while ( (devfn != pdev->devfn) && + (PCI_SLOT(devfn) == PCI_SLOT(pdev->devfn)) ); return rc; }